Apparatus and method for inter-chip or chip-to-substrate...

Details Apparatus and method for inter-chip or chip-to-substrate... Apparatus and method for inter-chip or chip-to-substrate...

2006-02-14

2006-02-14

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S108000, C438S109000, C257S685000, C257S686000, C257S777000

Reexamination Certificate

active

06998292

ABSTRACT:
The present invention is directed to a method and an apparatus where the standard wire bonding of TBGA's is replaced using a solid intermediate subcarrier on which the die may be flip chipped and which may then be flip chipped onto the substrate. The subcarrier has a number of conductors replacing the wire bond. In this manner, a better reflection suppression, better impedance matching, smaller conductor pitch and other advantages are achieved. The subcarrier may also be used for mounting multiple dies in a single substrate.

REFERENCES:
patent: 4346355 (1982-08-01), Tsukii
patent: 4995815 (1991-02-01), Buchanan et al.
patent: 5014161 (1991-05-01), Lee et al.
patent: 5266912 (1993-11-01), Kledzik
patent: 5294897 (1994-03-01), Notani et al.
patent: 5349495 (1994-09-01), Visel et al.
patent: 5406125 (1995-04-01), Johnson et al.
patent: 5459287 (1995-10-01), Swamy
patent: 5737187 (1998-04-01), Nguyen et al.
patent: 5832598 (1998-11-01), Greenman et al.
patent: 5869894 (1999-02-01), Degani et al.
patent: 6086383 (2000-07-01), Fasano et al.
patent: 6091147 (2000-07-01), Furuyama
patent: 6130483 (2000-10-01), Shizuki et al.
patent: 6137693 (2000-10-01), Schwiebert et al.
patent: 6143616 (2000-11-01), Geusic et al.
patent: 6194669 (2001-02-01), Bjorndahl et al.
patent: 6194750 (2001-02-01), Carroll et al.
patent: 6204448 (2001-03-01), Garland et al.
patent: 6211541 (2001-04-01), Carroll et al.
patent: 6215377 (2001-04-01), Douriet
patent: 6297551 (2001-10-01), Dudderar et al.
International Search Report dated Jun. 30, 2003 for International Application No. PCT/US02/38709, filed Dec. 02, 2002, mailed Jul. 23, 2003 (4 pages).

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