Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2003-07-29
2004-11-09
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C345S087000
Reexamination Certificate
active
06815976
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and a method for inspecting an array substrate of a liquid crystal display (LCD).
BACKGROUND OF THE INVENTION
An array substrate of an LCD in
FIG. 3
is a well-known array substrate which comprises: a substrate; a plurality of gate lines
12
provided on the substrate; a plurality of data lines
14
that cross the gate lines
12
through an insulating layer; switching elements
16
provided near the intersections of the gate lines
12
and the data lines
14
and connected to the gate lines
12
and the data lines
14
; pixel electrodes
18
connected to the switching elements
16
; storage capacitor (Cs) lines that form storage capacitors
26
by facing a part of the each pixel electrode
18
through an insulating layer; and gate-electrode capacitors
24
formed between the gate lines
12
and the pixel electrodes
18
. In this specification, the pixel electrode
18
is indium tin oxide (ITO).
Array substrates of an LCD are produced by etching and depositing various materials over and over again. They are inspected after the production, and non-defective ones are used in an LCD. As shown in
FIG. 3
, an inspecting apparatus
11
comprises: a gate voltage generating circuit
29
connected to a pad
34
of the gate line
12
through a probe
38
; a write circuit
30
for applying a write voltage to the data line
14
; a read circuit
32
for reading electric charges accumulated in the gate-electrode capacitor
24
and the storage capacitor
26
; a switch
42
for selecting the write circuit
30
or the read circuit
32
; and a probe
40
connected to the pad
36
of the data line
14
.
In general, the voltage applied to the pixel electrode
18
is &Dgr;V lower than a desired voltage to be applied, depending on the storage capacitor
26
and a liquid crystal capacitor. Such voltage difference &Dgr;V is hereinafter referred to as a “punch-through voltage”. If the punch-through voltages &Dgr;V of all the pixels are constant, the voltage to be applied to the pixel electrode
18
is increase by &Dgr;V so that all the pixels can function normally.
As the capacitance of the gate-electrode capacitor
24
increases due to foreign matter attached on the array substrate or defects in the array substrate, the punch-through voltage &Dgr;V gets higher than that of a normal pixel. This causes malfunctions of the LCD. For example, when electric charges are accumulated in the gate-electrode capacitor
24
and the storage capacitor
26
and then the switching element
16
is turned off, the electric charge accumulated in the storage capacitor
26
is transferred to the gate-electrode capacitor
24
and thus the storage capacitor
26
cannot retain desired electric charge.
If the amount of change in gate potential is &Dgr;Vg=(VGH−VGL) and a capacitance of a liquid crystal capacitor is Clc, the punch-through voltage &Dgr;V can be expressed by &Dgr;V=&Dgr;Vg×Cgd/(Cgd+Clc+Cs). In this specification, Cs and Cgd indicate capacitances of the storage capacitor
26
and the gate-electrode capacitor
24
, respectively, VGH and VGL indicate a voltage to be applied to the gate line
12
, and VGH is higher than VGL and turns on the switching element
16
.
An electric charge Q is measured as follows. As shown in FIG.
4
(
a
), an inspecting apparatus applies a gate voltage VGH. When the electric charges are written (T
1
), the conditions of the electric charges are expressed by Qgd=Cgd (VD−VGH) and Qcs=Cs (VD−VCs). In this specification, the phrase “electric charges are written” means that the electric charges Qgd and Qcs are accumulated in the gate-electrode capacitor
24
and the storage capacitor
26
, respectively. In addition, VD indicates a write voltage to be applied to the data line
14
shown in FIG.
4
(
b
) and Vcs indicates a voltage to be applied to the storage capacitor (Cs) line
20
.
When the electric charges are retained (T
2
), the conditions of the electric charges are expressed by Qgd=Cgd (VITO−VGL) and Qcs=Cs (VITO−VCs), wherein VITO indicates a voltage to be applied to the pixel electrode
18
.
When the electric charges are read (T
3
), the conditions of the electric charges are expressed by Qgd=Cgd (GND−VGH) and Qcs=Cs (GND−VCs), wherein GND indicates an earth potential.
The electric charge Q to be detected in the inspection of the array substrate are determined by subtracting the total amount of electric charges in a read operation from the total amount of electric charges in a write operation, and is expressed by Q=VD (Cs+Cgd). In the aforementioned expression, the capacitance of a data-electrode capacitor
44
shown in
FIG. 5
is neglected.
If Cs is 0.1 pF, Cgd is 0.01 pF, and a write voltage VD is 10V, the electric charge Q to be detected in a normal pixel is 1.1 pC.
In a defective pixel caused by a punch-through voltage failure, Cgd is 0.02 pF which is twice as much as that in a normal pixel. However, the electric charge Q detected in that defective pixel is 1.2 pC. Thus, the difference in electric charge between the normal pixel and the defective pixel is less than 10%, which is not sufficient enough to judge that Cdg falls outside a normal range, allowing for noise of the inspecting apparatus itself.
Further, it is also difficult to detect a capacitance of the data-electrode capacitor
44
shown in
FIG. 5
using the aforementioned technique, because no electric charges are accumulated in the data-electrode capacitor
44
in the write operation (T
1
) and therefore no electric charges are left in the read operation (T
3
).
More specifically, voltages to be applied to the gate line
12
and the data line
14
in the write and read operations are the same as those shown in FIG.
4
. If the capacitance of the gate-electrode capacitor
24
is neglected, an electric charge Qw in the write operation is expressed by Qw=Cs(VITO−VCs)+Cdd(VITO−VD) and an electric charge Qr in the read operation is expressed by Qr=Cs(GND−VCs)+Cdd(GND−GND). In the aforementioned expressions, Cdd indicates a capacitance of the data-electrode capacitor
44
. Therefore, the electric charge Q to be detected is expressed by Q=Cs(VITO−GND)+Cdd(VITO−VD).
If VGH is sufficiently high, for example, VD+5V or more, VITO=VD. Therefore, the electric charge Q to be detected is expressed by Q=(VITO−GND) and thus Cdd is not included. Since the capacitance of the data-electrode capacitor
44
cannot be detected during the inspection, even if the capacitance of the data-electrode capacitor
44
is not the normal value, the array substrate cannot be judged as defective.
Japanese Unexamined Patent Publication No. (Patent Kokai No.) 11-183550 (1999) discloses an apparatus for inspecting an array substrate. In this apparatus, an electric charge is accumulated in a pixel and then read after predetermined time. This is effective when a silicon etching residue is left between a pixel electrode and a common electrode. However, unlike the present invention, this publication does not disclose that a gate voltage is changed in write and read operations.
Accordingly, an object of the present invention is to provide an apparatus and a method for detecting a defective pixel caused by a punch-through voltage that cannot be detected by a conventional apparatus for inspecting an array substrate.
SUMMARY OF THE INVENTION
An apparatus for inspecting an array substrate according to the present invention comprises: means for applying a first voltage to switching elements so as to turn on the switching elements when electric charge is accumulated in storage capacitors and gate-electrode capacitors of the array substrate; and means for applying a second voltage having a different voltage value than the first voltage has to the switching elements so as to turn on the switching elements when the electric charge accumulated in the storage capacitors and the gate-
Dougherty Anne V.
International Business Machines - Corporation
Jennings Derek S.
Karlsen Ernest
LandOfFree
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