Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-01-15
2003-07-08
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230060, C365S194000
Reexamination Certificate
active
06590828
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and a method for inputting address signals in semiconductor memory device; and, more particularly, to an apparatus and a method for inputting address signals in semiconductor memory device to avoid the damage of the cell data caused by the change of address signals before a restore and to reduce the stand-by current.
BACKGROUND OF THE INVENTION
Generally, the dynamic random access memory (DRAM) is widely known as a semiconductor memory device having a memory cell with the capacitor. Since the DRAM includes one access transistor and one capacitor, the DRAM is advantageous in high integration. However, in order to maintain the data stored in the cell, the refresh is required periodically in the DRAM. On the other hand, although the refresh is not required in the static RAM(SRAM) because it operates in a latch type, however, it has disadvantage that the integration is not high as the DRAM because a unit cell has to include the a plurality of transistors.
The pseudo SRAM and the virtual SRAM are widely known for the devices having the advantages of both DRAM and SRAM devices. Although a capacitor is used to store data in a cell, the refresh is concealed easily in both the pseudo SRAM and the virtual SRAM.
However, in case of using the capacitor as a cell, a restriction is imposed on the restore because the address signals should not be changed until the data is restored on the capacitor. Particularly, a tRAS control signal is used in the DRAM in order that new addresses are inputted after restoring enough data in the cell. However, the SRAM does not have such tRAS specification, an apparatus and a method are necessary to guarantee an input of new address after restoring enough data in the cell.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus and method for address input device in the semiconductor memory device.
In accordance with an aspect of the present invention, there is provide an apparatus for inputting address signals in a semiconductor memory device having a unit cell including a capacitor, comprising: an internal clock generating means for generating and outputting an internal clock signal at a fixed period; and a buffering and sampling means for buffering input address signals and sampling input address signals at the fixed period in response to the internal clock signal.
In accordance with another aspect of the present invention, there is provide a method for inputting address signals in a semiconductor memory device having a unit cell including a capacitor, comprising the steps of: buffering an input address signal applied from a pad; generating an internal clock signal at a fixed period; and sampling the fixed period by using the buffered input address signal as the internal clock signal.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
REFERENCES:
patent: 5844857 (1998-12-01), Son et al.
patent: 6154415 (2000-11-01), Jeong
Coremagic Inc.
Harness & Dickey & Pierce P.L.C.
Hoang Huan
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