Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2001-08-24
2003-12-16
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C327S115000, C327S117000
Reexamination Certificate
active
06665368
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
FIELD OF THE INVENTION
The present invention is generally directed to frequency dividers. More particularly, the present invention is directed to increasing the maximum input frequency of a frequency divider.
BACKGROUND OF THE INVENTION
The division of frequency in operations of the electronic circuitry has long been known in the art. Presently, a number of electronic circuitry utilize various frequency division methods and formulas, such as direct frequency division using conventional flip-flop circuitry, to transmit and alter the output frequencies of various electronic devices.
These devices, however, are not without shortcomings. Existing frequency dividers are each limited to a predetermined maximum input frequency which can be received by the divider while performing any frequency division task. This limitation is in part due to topology used to design the component as well as each device being limited to a predetermined integral division ratio number, such as integer 2, by which it divides its received frequencies. The foregoing shortcomings in the existing frequency dividers generally undesirably limits the operation of the devices which utilize an existing divider by lowering the maximum frequency which can be inputted into the device.
Currently, one method of minimizing this limitation is in the use of multiple dividers. In this approach, multiple dividers are operatively connected to each other to virtually aggregate the maximum input frequency of each divider into an overall multiple divider combination having increased maximum input frequency. This allows for the overall multiple divider combination to accommodate a signal whose frequency is greater than the frequency of each individual divider. This solution however, is less than favorable because of the inherent disadvantages associated with the use of multiple divider. The use of multiple dividers adds to the complexity, size and associated cost in the manufacturing of the underlying device. In addition, use of multiple dividers undesirably increases signal noise and reduces the speed of operations due to increased number of circuitry, which in turn increases the overall processing time of the underlying device. Furthermore, power consumption is unfavorably increased resulting in reduced efficiency in power consumption and other associated problems such as additional thermal dissipation that can increase the noise levels in the processed signal. Finally, the addition of extra dividers at a later post manufacturing stage may not be possible, especially if the entire circuit layout is embedded on a microchip.
It is therefore an object of the present invention to provide an electronic a device that can advantageously increase the frequency inputted into a frequency divider device during any frequency division task.
It is another object of the present invention to provide an electronic a device that can convert the divider ratio from an even ratio to an odd ratio, or from an odd ratio to an even ratio during any frequency division task, in a manner that would increase the overall maximum frequency inputted into the device.
SUMMARY OF THE INVENTION
These and other objects are achieved by the various apparatus and associated methods of the present invention.
In a broad aspect, the present invention provides a novel apparatus for increasing the maximum input frequency of a frequency divider. The apparatus includes a frequency mixer circuit to receive as input a first input frequency signal, a second input frequency signal and to generate a combination signal wherein the combination is a frequency subtraction of the second input frequency signal from the first input frequency signal, at least one frequency divider circuit in operative contact with the mixer to receive and to frequency divide the combination frequency signal by a predetermined number.
The apparatus further includes at least one of a signal splitter and a directional coupler in operative contact with the frequency divider to receive the divided frequency signal and to generate an output frequency signal and a feedback frequency signal wherein the feedback signal having a frequency identical with the output frequency signal and wherein the feedback frequency signal constitutes the second input frequency signal.
In another aspect, the present invention provides a method for increasing the maximum input frequency of a frequency divider system. The method includes communicating an input frequency signal to be frequency divided to a mixer input, communicating an output of the mixer to a frequency divider input generating an output frequency signal; and feeding the divider output frequency signal back into the mixer for combination with the input frequency signal whereby the input frequency signal and the divider output frequency signal are mixed in a frequency subtractive manner such that the mixer output to the frequency divider unit is at a lower frequency than the input signal frequency, causing the divider output frequency signal to be at a lower frequency than if the divider was connected directly to the input signal.
A more detailed understanding of these features, and of additional features, objects, and advantages of the present invention will be provided to those skilled in the art from a consideration of the following Detailed Description of the Invention, taken in conjunction with the accompanying Drawings, which will now first be described briefly.
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patent: 4721905 (1988-01-01), Mehrgardt
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patent: 6020790 (2000-02-01), Jackson
patent: 6323991 (2001-11-01), Cisternino et al.
Stubbs et al., “A Single Stage Monolithic Regenerative 1/2 Analog Frequency Divider”, 1996, Department of Communication, Communications Research Centre, pp. 1999-201.*
M.G. Stabbs & S.P. Stapleton, A Single Stage Monlithic Regenerative 1/2 Analog Frequency Divider, 1996, pp. 199-201, Department of Communication, Communications Research Centre, 3701 Carling Avenue, Ottawa, Ontario
Northrop Grumman
Stetina Brunda Garred & Brucker
Wambach Margaret R.
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