Apparatus and method for improving the timing performance of a c

Details Apparatus and method for improving the timing performance of a c Apparatus and method for improving the timing performance of a c

1994-01-28

1995-06-20

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054265916

ABSTRACT:
A computer aided design system and method for automatically modifying a specified Hardware Description Language (HDL) characterization of a circuit to reduce signal delays on critical paths of the circuit is described. The specified circuit is analyzed with a logic synthesizer including a novel cell-based timing verifier that determines if a circuit meets specified timing requirements. Timing requirements are tested by computing a slack value for each node of the circuit at the component (macrocell) level, where the slack value represents the difference between the required arrival time of a signal at each circuit node and the computed worst case signal arrival time for the node. The output node having the most negative slack value is identified as a critical node. The HDL description of the circuit corresponding to the critical node is modified with a synthesis directive to substitute the original datapath cell with a better cell in order to improve the circuit's timing performance. The revised HDL description of the circuit is then re-synthesized. Improvements to the circuit may be repeated in this fashion until the circuit meets all timing constraints.

REFERENCES:
patent: 5197015 (1993-03-01), Hartoog et al.
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5282148 (1994-01-01), Poirot et al.
patent: 5311443 (1994-05-01), Crain et al.

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