Static information storage and retrieval – Floating gate – Particular biasing
Patent
1989-11-21
1991-06-25
Gossage, Glenn
Static information storage and retrieval
Floating gate
Particular biasing
36518909, 36523006, G11C 1606
Patent
active
050273213
ABSTRACT:
An apparatus and method for improved reading/programming of a virtual ground EPROM array includes a selected memory cell within the array which is accessed so as to avoid parasitic current flow in adjacent cells by first selecting the row line coupled to the control gate electrode of the selected cell. Next, a first column line coupled to the source of the selected cell is grounded. A second column line is coupled to the drain of the selected cell and a third column line is coupled to the drain of the adjacent cell. Simultaneously, a first potential is applied to the second column line to conditionally flow a read current through the selected cell while the second potential is applied to the third column line to shield the adjacent cell from parasitic current. To avoid disturbance of adjacent cells during programming, the array is effectively debiased utilizing intercolumn pass gates along with slow ramping of the selected column voltage.
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patent: 4237547 (1980-12-01), Smith
patent: 4387447 (1983-06-01), Klaas et al.
patent: 4639893 (1987-01-01), Eitan
patent: 4722075 (1988-01-01), Kaszubinski et al.
patent: 4723225 (1988-02-01), Kaszubinski et al.
patent: 4868790 (1989-09-01), Wilmoth et al.
Gossage Glenn
Intel Corporation
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