Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-06-28
2011-06-28
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
C716S101000, C713S500000
Reexamination Certificate
active
07971161
ABSTRACT:
A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.
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Blaner Bartholomew
Brown Mary D.
Burky William E.
Venton Todd A.
Cantor & Colburn LLP
Dimyan Magid Y
International Business Machines - Corporation
LeStrange Michael
Whitmore Stacy A
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