Apparatus and method for implementing a multiplexer

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output

Reexamination Certificate

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C327S403000

Reexamination Certificate

active

06489830

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to digital logic circuits and more specifically to an apparatus and method for implementing a multiplexer.
BACKGROUND OF THE INVENTION
Multiplexers are used extensively in many applications such as computers and telecommunications. For example, multiplexers comprise the primary portion of the register file in a field-programmable-gate-array (FPGA) implementation of a microprocessor. The problem sometimes arises, however, that the multiplexer function does not map efficiently onto four-input look-up tables, which are the basic logical building block of many FPGAs. Specifically, some FPGA synthesis tools use additional logic available in the majority of FPGAs to fit, for example, a four-to-one multiplexer into two four-input look-up tables. Unfortunately, use of this additional logic makes it unavailable for other uses and complicates the process of placement and routing. It is thus apparent that there is a need in the art for an improved multiplexer implementation.
SUMMARY OF THE INVENTION
An apparatus and associated method are provided for implementing a multiplexer. The multiplexing function is divided into two stages, the first of which outputs either a selection result or a selection signal. The selection result corresponds to one of a first set of data inputs to the first stage. The second stage selects one of a second set of data inputs to the second stage in response to the selection signal.


REFERENCES:
patent: 4926423 (1990-05-01), Zukowski
patent: 6118300 (2000-09-01), Wittig et al.
patent: 6124736 (2000-09-01), Yamashita et al.
Yamashita, S. : Performance-Driven Functional Decomposition And Circuit Minimization, Last Modified: Wed, Oct. 14, 1998, pp. 1-2.

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