Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2006-08-03
2010-06-15
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S003200, C386S349000, C348S441000, C348S513000
Reexamination Certificate
active
07737960
ABSTRACT:
A source frame signal received at a first frame rate is converted to a destination frame signal output at a second frame rate. By adjusting the clock frequency of the clock signal in the destination frame signal, the second frame rate is made to be the same as the first frame rate. Adjusting the destination clock frequency prevents overflow and underflow conditions. The destination clock frequency is decreased to prevent underflow or increased to prevent overflow. The destination clock frequency during the last horizontal line is adjusted to comply with some display devices having a maximum time constraint from a last horizontal sync signal to a vertical sync signal in the destination frame signal.
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Chen Issac
Gong Jin-Sheng
Hjerpe Richard
Realtek Semiconductor Corp.
Thomas Kayden Horstemeyer & Risley
Webb Dorothy
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