Apparatus and method for identifying exception routines indicate

Details Apparatus and method for identifying exception routines indicate Apparatus and method for identifying exception routines indicate

1998-03-06

2000-04-18

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

714 38, 714 39, 714 45, 714 54, G06F 1100

Patent

active

060527749

ABSTRACT:
The present invention provides a debugger interface unit for a data processing apparatus, comprising a control register having a number of fields, each field corresponding to a particular exception routine, and each field being settable to indicate that the debugger wishes to identify an access to the corresponding exception routine. Further, an exception routine catch logic is provided to receive a first signal when a processor core within the data processing apparatus issues an instruction fetch command for an exception routine, and to determine from an instruction address issued with the instruction fetch command which exception routine is being fetched. In addition, the catch logic is arranged to reference the field of the control register corresponding to the determined exception routine to determine if that field has been set, and if the field has been set, to output a breakpoint signal to the processor core.
The above approach provides a particularly efficient technique for identifying accesses to exception routines when debugging software, such identification being independent of the base address of the exception routines.

REFERENCES:
patent: 5390305 (1995-02-01), Takahashi et al.
patent: 5537559 (1996-07-01), Kane et al.
patent: 5680620 (1997-10-01), Ross
patent: 5745770 (1998-04-01), Thangadurai et al.
patent: 5857094 (1999-01-01), Nemirovsky

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