Apparatus and method for high speed shifting of test data throug

Details Apparatus and method for high speed shifting of test data throug Apparatus and method for high speed shifting of test data throug

1996-02-22

1997-10-28

Nguyen, Hoa T.

Excavating

G01R 3128

Patent

active

056823916

ABSTRACT:
High speed shifting of test data through an integrated circuit is achieved by modifying the output portion of a circuit, while still observing relevant test standard protocols, such as the Joint Test Access Group, IEEE Std. 1149.1, entitled IEEE Standard Test Access Port and Boundary-Scan architecture. An output signal generated during a first signal transition of a first clock cycle is passed through a large output multiplexer with a long path delay. A cycle-insertion switching element is connected to the output node of the output multiplexer. The cycle-insertion switching element generates an output signal in response to a first signal transition of a second clock cycle. An output switching element applies the output signal to an output pin in response to a second signal transition of the second clock cycle. A second multiplexer is used to select the output signal from either the output multiplexer or the cycle-insertion switching element. The output signal from the output multiplexer is selected at lower clock speeds when the signal delay through the output multiplexer is not critical. The output signal from the cycle-insertion switching element is selected at higher clock speeds to insure that the output switching element receives the output signal before the second signal transition of the additional clock cycle.

REFERENCES:
patent: 5198999 (1993-03-01), Abe et al.
patent: 5281864 (1994-01-01), Hahn et al.
patent: 5343425 (1994-08-01), Saito et al.
patent: 5355369 (1994-10-01), Greenbergerl et al.

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