Apparatus and method for high speed 2D/3D image...

Computer graphics processing and selective visual display system – Computer graphics processing – Graph generating

Reexamination Certificate

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Reexamination Certificate

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06239812

ABSTRACT:

DESCRIPTION
1. Technical Field
The invention applies to the field of image processing and specifically refers to an apparatus and method for manipulating bit mapped images with a fast hardware engine capable of processing images on a pixel by pixel basis and capable of providing image 2D/3D translation, rotation, panning, zooming and shrinking at a high speed rate due to the pipelined implementation of such hardware.
This hardware engine can be suitably interfaced to a host graphic workstation bus system to give the host the capability of performing real time image transformation and display functions. It is the intent of the present invention to have the ability of processing monoband and multiband images (i.e. RGB) of any size (up to 2048×2048 pixels or larger) in a few tenths of second.
2. Background Art
It is known and usual to implement the functions provided by the present invention by software with time consuming processes.
EP-A 0367418 by J.Gonzalez-Lopez describes an hardware engine that implements an image interpolation function providing a high speed zoom capability to an image display system by using a bidimensional filter. The apparatus disclosed employs a bilinear interpolation algorithm implemented in the form of cascaded one dimensional interpolation circuits. It provides a single function of image magnification.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to overcome the above described drawbacks of the prior art by providing a high speed image processing system more flexible than the previous known similar systems. This capability is due to the presence of a local microprocessor capable of handling the parameters without adding any significant overhead to the hardware performances while performing the functions of image 2D/3D translation, rotation, panning, zooming and shrinking. The present hardware solution allows a significant performance improvement while adding an innovative solution. This innovative solution includes decomposing a complex image transformation into one or more simple passes with the aid of a work storage, a read path from this storage to pixel buffers, a color look-up table (CLUT) function and an averaging mechanism.
Another object of the present invention is to provide a work storage which can be smaller than the processed image, thereby saving hardware costs. To achieve this savings, the source image can be processed in several subsequent portions (called ‘slices’) which match the work storage size. This means that the overall passes for each image transformation must be repeated for each slice. On the other hand, the work storage size does not significantly impact the process speed and the image quality.
It is another object of this invention to provide an apparatus and method for obtaining 2D/3D image transformation functions with improved image quality.
Another object of the present invention is the possibility to “read back” a bit mapped image from the destination pixel memory to the source memory since the channel between the two memories is bidirectional.
These and other objects, as will result evident by the description, are achieved by manipulating bit mapped images on a pixel by pixel basis. This provides 2D/3D image translation, rotation, panning, zooming and shrinking through a hardware pipeline implementation and a local microprocessor. The local microprocessor controls the execution of the transformation without significantly adding any overhead to the hardware performances.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.


REFERENCES:
patent: 4545069 (1985-10-01), Kermisch
patent: 5097430 (1992-03-01), Birang
patent: 5157766 (1992-10-01), Butler et al.
patent: 5201035 (1993-04-01), Stytz et al.
patent: 5293481 (1994-03-01), Mita et al.
patent: 5327527 (1994-07-01), Hatayama
patent: 5404445 (1995-04-01), Matsumoto
patent: 0367418 (1990-05-01), None
patent: 0396517 (1990-11-01), None
patent: 2244887 (1991-12-01), None

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