Image analysis – Learning systems – Neural networks
Reexamination Certificate
2008-06-06
2011-12-20
Strege, John (Department: 2624)
Image analysis
Learning systems
Neural networks
C706S015000
Reexamination Certificate
active
08081816
ABSTRACT:
The present invention is an apparatus and method for object recognition from at least an image stream from at least an image frame utilizing at least an artificial neural network. The present invention further comprises means for generating multiple components of an image pyramid simultaneously from a single image stream, means for providing the active pixel and interlayer neuron data to at least a subwindow processor, means for multiplying and accumulating the product of a pixel data or interlayer data and a synapse weight, and means for performing the activation of an accumulation. The present invention allows the artificial neural networks to be reconfigurable, thus embracing a broad range of object recognition applications in a flexible way. The subwindow processor in the present invention also further comprises means for performing neuron computations for at least a neuron. An exemplary embodiment of the present invention is used for object recognition, including face detection and gender recognition, in hardware. The apparatus comprises a digital circuitry system or IC that embodies the components of the present invention.
REFERENCES:
patent: 5253330 (1993-10-01), Remacher et al.
patent: 5533169 (1996-07-01), Burnod et al.
patent: 5799134 (1998-08-01), Chiueh et al.
patent: 5956703 (1999-09-01), Turner et al.
patent: 6324532 (2001-11-01), Spence et al.
patent: 6836767 (2004-12-01), McBride
patent: 7099510 (2006-08-01), Jones et al.
patent: 7840037 (2010-11-01), Lu et al.
Irick et al. A unified streaming architecture for real time face detection and gender classification, 2007, IEEE.
Irick et al. A real time embedded face dectector on FPGA, Signals, Systems and Computers, 2006, pp. 917-920.
T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, and V. Srikantam, “A Generic Reconfigurable Neural Network Architecture Implemented as a Network on Chip,” in the Proceedings of the IEEE System on Chip Conference (SoCC, formerly ASIC), 2004.
Irick Kevin Maurice
Jung Namsoon
Moon Hankyu
Narayanan Vijaykrishnan
Sharma Rajeev
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