Apparatus and method for handling string operations in a pipelin

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364DIG1, 364DIG2, G06F 1300

Patent

active

054044731

ABSTRACT:
In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a pre-determined number of iterations to be issued into the pipeline. Following the instruction, the pre-determined number of iterations are issued to the pipeline. When the instruction returns with the calculated number, the instruction sequencer then knows exactly how many iterations should be executed. Any extra iterations that had initially been issued are canceled by the execution unit, and additional iterations are issued as necessary. A loop counter in the instruction sequencer is used to track the number of iterations.

REFERENCES:
patent: 4882701 (1989-11-01), Ishii
patent: 5056004 (1991-10-01), Ohde et al.
patent: 5101484 (1992-03-01), Kohn
patent: 5265253 (1993-11-01), Yamada
patent: 5303355 (1994-04-01), Gergen et al.

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