Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-10-07
2001-09-11
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000, C345S111000, C345S182000, C345S156000, C348S714000, C348S715000, C348S716000
Reexamination Certificate
active
06288698
ABSTRACT:
FIELD OF INVENTION
Invention relates to computer graphics, particularly to electronics for controlling flat-panel display gray-scale and brightness.
BACKGROUND OF INVENTION
Super Twisted Nematic Liquid Crystal Displays (STN LCDs) are fundamentally binary devices for displaying gray scale by combining temporal modulation (e.g., Frame Rate Control (FRC)) and spatial modulation (e.g., dither) techniques. Since dither reduces spatial resolution, temporal modulation is preferred to produce gray scaling. However, temporal FRC approach for gray scale produces visual artifacts, such as flicker, due to temporal sensitivity of the human visual system (HVS). Accordingly there is need for achieving high quality, such as 256, gray level frame rate control in simple and elegant manner, thereby eliminating need for conventional spatial dither which introduces objectionable patterns.
In particular, such need would be especially appropriate to provide desired improvement over conventional brute-force approach to 256 gray-scale graphics processing, for example, wherein 256×256 weight table (i.e., corresponding to storing “1” or “0” for each of 256 frames (i.e., rows) and 256 gray levels (i.e., columns)) is ordinarily employed to achieve FRC digital signal processing.
SUMMARY OF INVENTION
Subject invention arises in electronic apparatus and signal processing method for gray scale and brightness display control, which effectively avoid use of weight table approach with frame rate control, particularly by generating specified phases (e.g., 256) of tiling pattern (e.g., 16×16) on-fly, preferably using 4×4 upper bank and 4×4 lower bank pattern memory. Row and column counts are provided in specified (“new”) coset hash function which generates random phase used to index upper 4×4 pattern memory. Random phase may be scrambled using upper 4×4 pattern memory. Lower 4×4 pattern memory is provided by row and column counts to generate novel 256 phase number addressing scheme. Upper memory output is used as upper 4 most significant bit (msb) whereby output of lower memory are used, as lower 4 msb of 8-bit phase number. Such bit phase number is received by FRC data generator block for comparison to selected value range (e.g., as generated using frame count and data value,) to decide whether output bit is “
1
” or “0”.
Preferably, such logic may be applied to upper and lower STN display areas for dual-scan panels. FRC data generator block is applied per primary color, i.e., one each for red, green, and blue. Red and blue FRC data generators may be identical to green, except that output is offset by adding red and blue offset, respectively, to frame count before use in FRC data generator, thereby providing even distribution of phase between red, green, and blue, pixels.
REFERENCES:
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patent: 5552800 (1996-09-01), Uchikoga et al.
patent: 5805126 (1998-09-01), Bassetti
patent: 6008794 (1999-12-01), Ishii
patent: 6078361 (2000-06-01), Reddy
Ishii Takatoshi
Park Yonggab
Carr & Ferrell LLP
Nguyen Jimmy H.
S3 Graphics Co., Ltd.
Shalwala Bipin
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