Apparatus and method for generating timing signals for latched t

Details Apparatus and method for generating timing signals for latched t Apparatus and method for generating timing signals for latched t

1976-03-31

1977-11-29

Thomas, James D.

Boots, shoes, and leggings

365233, G06F 1300

Patent

active

040607941

ABSTRACT:
Apparatus and a method for generating timing signals to be utilized in latched type memories only when the address signals are valid. A CAS signal is generated in response to an RAS signal via a device which tracks the worst case delay of memory address signals and does not permit the application of the CAS signal to memory until the worst case delay of the memory address signals has been accounted for.
A memory array is comprised of any combination of latched or non-latched tri-state memories. The latched memories are coupled to a data bus utilizing conventional TTL circuits in combination with a power driver to simulate conventional tri-state buffer circuits. When the power driver/drivers remove(s) power from TTL circuits, the tri-state characteristics are simulated; whereas when the power driver applies power to the TTL circuits, they operate in their normal mode and present a normal impedance between the data bus and data-out lines of the memory array.

REFERENCES:
patent: 3809884 (1974-05-01), Nibby
patent: 3969706 (1976-07-01), Proebsting

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