Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-04-21
2004-07-20
Chin, Stephen (Department: 2734)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S255000, C714S728000, C714S781000, C714S739000, C375S130000
Reexamination Certificate
active
06766337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a device and method for generating spreading code in a CDMA communication system, and in particular, to a device and method for generating spreading code for spread spectrum.
2. Description of the Related Art
In an existing IS-95 CDMA system, spread spectrum is performed at a chip rate of 1.2288×10
6
cps (chips per second), so that a short PN (Pseudo Noise) code is generated at the chip rate of 1.2288×10
6
cps Since the short PN code should be generated during one-frame period (80 msec/3≡26.67 msec) of a sync channel, the short PN code has a period of 2
15
chips (1.2288×10
6
cps*0.02667 sec).
FIG. 1
shows a conventional device for generating spreading codes. Referring to
FIG. 1
, the spreading code generator generates a short PN code using a generator for generating an ML sequence (M-sequence and/or Maximal-Length sequence, hereinafter the two terms will be used interchangeably) of length 2
15
−1. The generator is comprised of 15 shift registers labeled R
1
-R
15
. By inserting one ‘0’ after 14 ‘0’ sequences IS-95 standard identifies two phase channels (i.e., In-phase and Quadrature-phase channels) that use different polynomials and employ two different ML sequences.
A short PN code having a delay effect by a specific period &Dgr; with regard to the generated short PN code can be obtained by selectively module-2 adding the shift register values of the generator polynomial. That is, in
FIG. 1
, modulo-2 adders
101
-
104
modulo-2 add outputs of their associated shift registers R
1
-R
15
to the outputs of their associated AND gates
122
-
125
, and provide their outputs to shift registers in the next stages. To select a shift register value for modulo-2 adding, a mask Short_PN_Code_Mask[0:14] is used. That is, different mask values are applied to generate short PN codes having a different offset (or phase difference).
A proposed IMT-2000 system based upon a CDMA-2000 system supports a wideband CDMA system having a spreading frequency bandwidth greater than 1.2288×10
6
cps. For a short PN code used in this case, 2
S
−1 (where S is a positive number) sequences are partially selected from an ML sequence of length 2
15
×N (where N is a 3 or a multiple of 3) which is not the conventional ML sequence of 2
15
−1. Table 1 below shows a length of the short PN code required for each chip rate.
TABLE 1
Length (P) of Short
Spread Spectrum
PN Code during
(Chip Rate)
1-Frame of Sync CH
(M-sequence Length:
N
= 1.2288 × 10
6
× N
p = 2
15
chip × N
2
8
− 1)
1
1.2288 × 10
6
2
15
chip
(2
15
− 1)
3
1.2288 × 10
6
× 3
2
15
× 3 chip
(2
17
− 1)
6
1.2288 × 10
6
× 6
2
15
× 6 chip
(2
18
− 1)
9
1.2288 × 10
6
× 9
2
15
× 9 chip
(2
19
− 1)
12
1.2288 × 10
6
× 12
2
15
× 12 chip
(2
19
− 1)
Although an offset delay value for identifying the base station is applied to the generated short PN code, only the partially selected sequence should occur. However, in the conventional method in which an offset-delayed short PN code is generated by simply applying one mask, a sequence departing from the selected ML sequence period may be generated undesirably.
Such problems will be described with reference to FIG.
2
.
FIG. 2
shows a method for determining a short PN code having a length p=2
15
×3 from an ML sequence having a length m=2
17
−1 represented by (b). Assume that the method for generating the spreading code having a length 2
15
×3 shown in
FIG. 1
is expanded to generate a short PN code by selecting only the first ¾ portion from an ML sequence of length 2
17
−1, in which 17 shift registers are provided. Assuming that a value selected from one period value of the binary ML sequence represented by (b) is C
0
and a short PN code is generated by selecting sequence values of length p beginning at the sequence value C
0
, the remaining (m−p) sequences out of the total m ML sequences correspond to an unused sequence. There is a simple method for generating the short PN code by selecting a partial period of the whole ML sequence. In this method, a present state, represented by (d), of the shift register for generating the ML sequence or a sequence output is monitored. Further, after the state of the shift register becomes S
p−1
as represented by (d) of
FIG. 2
, or after a (p−1)th sequence occurs, an initial state signal represented by (c) is generated to initialize the shift register so that the first sequence C
0
is output.
A description will be made regarding a phenomenon occurring when only one mask value Mask_r corresponding to ‘r’ is applied as shown in
FIG. 1
to apply an offset delay ‘r’ to the generated short PN code represented by (e) of FIG.
2
. In this case, as shown by (f) of
FIG. 2
, the offset delay value ‘r’ is applied to the ML sequence value in an A period corresponding to the sequences from 0
th
sequence to an (r−1)th sequence to generate (m−r)th to (m−1)th sequence values out of the original whole ML sequence of length ‘m’, and generate 0
th
to (p−r−1)th ML sequence vales from rth to (p−1)th ML sequences. This is because based on a unique property of the ML sequence, the offset delay value is determined according to the present shift register state and the mask value, and since a period of the original ML sequence is ‘m’, the offset delay occurs based on this period. Therefore, (m−r)th to (m−1)th ML sequence values belonging to the unused period occur in the A period. The presence of the sequence values in the A period is against the original intention of cyclic delaying only the original ML sequence values of 0
th
sequence C
0
to (p−1)th sequence C
p−1
. That is, to achieve the desired cyclic offset delay as represented by (g) of
FIG. 2
, the offset delay value ‘r’ is applied to 0th to (r−1)th ML sequence values C
0
-C
r−1
so as to generate (p−r)th to (p−1)th sequence values of the original ML sequence.
As described above, when the conventional spreading code generation method generates a short PN code using only one mask, the undesired output is obtained in the A period of FIG.
2
. To solve such problems, there is required a mask, Mask_(m−p+r), for further delaying by ‘m−p’ which corresponds to a length of the unused sequence of the original ML sequence, instead of using the mask Mask_r for delaying by ‘r’ in the A area.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a device and method for generating a short PN code for spread spectrum in a CDMA communication system.
It is another object of the present invention to provide a device and method for generating a spreading code having a short period from a sequence having a long period in a CDMA communication system.
It is further another object of the present invention to provide a spreading code generation device and method which uses at least two masks in consideration of an offset so that an unused sequence period out of the whole sequence having a long period should not occur in the spreading code having the offset, in a CDMA communication system.
To achieve the above object, there is provided a device for generating a spreading code in a CDMA communication system. In the device, an ML (Maximal Length) sequence generator generates an ML sequence according to a generator polynomial of an ML sequence having a length 2
S
−1 and a given initial value, and reloads the initial value whenever an ML sequence having a length shorter than the length 2
S
−1 is generated, to repeatedly perform an operation of generating the ML sequence. A mask selector including first and second masks having a given offset, selects the first mask in an ML sequence period of the desired length a
Bae Sang-Min
Cho Mi-Young
Chin Stephen
Dilworth & Barrese LLP
Ha Dac V.
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