Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2008-05-20
2008-05-20
Mai, Tan V. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
10765497
ABSTRACT:
An apparatus for performing an MultiMedia extension (MMX) Packed Sum of Absolute Differences (PSADBW) instruction is disclosed. The apparatus includes carry-generating subtraction logic that generates packed differences of the subtrahend from the minuend and associated carry bits indicating whether the difference is positive or negative. The apparatus selectively inverts the differences based on the carry bits. Addition logic adds the selectively inverted differences and carry bits substantially in parallel to generate the PSADBW instruction result. In one embodiment, the apparatus also includes two muxes. The first mux selects the selectively inverted differences in the case of a PSADBW instruction and selects a multiply instruction's partial products otherwise. The second mux selects the carry bits in the case of a PSADBW instruction and selects a second multiply instruction's partial products otherwise. The two mux outputs are provided to the addition logic. In one embodiment, the microprocessor translates the PSADBW instruction into at least first and second microinstructions for execution.
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Johnson Daniel W. J.
Loper Albert J.
Davis E. Alan
Huffman James W.
Mai Tan V.
VIA Technologies Inc.
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