Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2005-09-13
2005-09-13
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230010
Reexamination Certificate
active
06944088
ABSTRACT:
A sum decoder is disclosed including multiple sum predecoders, a carry generator, and multiple rotate logic units. Each sum predecoder receives multiple bit pairs of non-overlapping segments of a first and second address signal, and produces an input signal dependent upon the bit pairs. The carry generator receives a lower-ordered portion of the first and second address signals, and generates multiple carry signals each corresponding to a different one of the sum predecoders. Each rotate logic unit receives the input signal produced by a corresponding sum predecoders and a corresponding one of the carry signals, rotates the bits of the input signal dependent upon the carry signal, and produces either the input signal or the rotated input signal as an output signal. A memory is described including the sum decoder, a final decode block, and a data array. The final decode block performs logical operations on the output signals of the sum decoder to produce selection signals. Each of the selection signals activates a word line of the data array. A method is disclosed for producing signals for accessing a memory. Highest ordered portions of the first and second address signals are divided into multiple non-overlapping segments. An input signal (i.e., an I term) is generated for each of the segments, as is a carry signal. For each of the segments, when the corresponding carry signal is set, the corresponding I term is rotated one bit position. The I terms are produced as the signals.
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Asano Toru
Dhong Sang Hoo
Silberman Joel Abraham
Takahashi Osamu
Auduong Gene N.
Carr LLP
Gerhardt Diana R.
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