Apparatus and method for generating integrated circuit test patt

Details Apparatus and method for generating integrated circuit test patt Apparatus and method for generating integrated circuit test patt

1997-03-26

1998-04-28

Beausoliel, Jr., Robert W.

Excavating

371 271, 371 274, G06F 1100

Patent

active

057455015

ABSTRACT:
A method and apparatus for generating integrated circuit test patterns (218) to test a functionality of integrated circuits. Module test stimuli (202) for each module present in an integrated circuit (10) are generated and retained (102). The module test stimuli (202) are translated to module drive patterns (206). Module expected patterns (210) are determined based on the module drive patterns (206) or module test stimuli (202) using module models (208). Integrated circuit data (216) describing the structure and timing of the integrated circuit (10) is used to translate the module patterns (212) into integrated circuit test patterns (218). The integrated circuit test patterns (212) are validated (220), transformed to test vectors (226), and the test vectors (226) are applied to the external connections of the integrated circuit (10) to test a functionality of the integrated circuit (10). A data processing system (300) creates the integrated circuit test patterns (218). The steps of the present invention are incorporated into a computer readable medium and a method for manufacturing and testing an integrated circuit (10).

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patent: 5475624 (1995-12-01), West
patent: 5477545 (1995-12-01), Huang

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