Static information storage and retrieval – Powering
Reexamination Certificate
2003-01-07
2003-11-25
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Powering
C365S189050, C365S233100, C331S060000
Reexamination Certificate
active
06654306
ABSTRACT:
TECHNICAL FIELD
The present invention relates to voltage generating circuits, and, more particularly, to a method and circuit for providing a plurality of oscillating signals that can be used for generating a pumped output voltage.
BACKGROUND OF THE INVENTION
In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, a typical application of a charge pump circuit is in a conventional dynamic random access memory (“DRAM”), to generate a boosted word line voltage VCCP having an amplitude greater than the amplitude of a positive supply voltage VCC or a negative substrate or back-bias voltage Vbb that is applied to the bodies of NMOS transistors in the DRAM. A charge pump may also be utilized in the generation of a programming voltage VPP utilized to program data into memory cells in non-volatile electrically block-erasable or “FLASH” memories, as will be understood by those skilled in the art.
A conventional charge pump circuit is illustrated in
FIG. 1
a
. A voltage regulator monitors the voltage level and activates an oscillator to drive or boot the pump stage when a boosted voltage VCCP needs to be produced. Several designs of oscillators and pump stages are well known in the art. In designing charge pump circuits, not only do charge pumps need to be able to generate sufficient voltage levels, but the circuits should also be designed to produce the boosted voltage with sufficient drive capability in an efficient and reliable manner. These features become more important as operating voltages continue to decrease, as well as the increasing demand for devices having charge pump circuits that consume less power.
One approach that has been taken in designing charge pump circuits that can provide boosted voltages with sufficient drive capability is to use a plurality of pump stages operating in parallel. In order to minimize the size of the circuitry, the plurality of pump stages are driven by a common oscillator circuit that provides a signal to the input of each of the pump stages. However, as a result of the pump stages being driven in by a common signal, extreme peak current values may occur when the pump stages are initially enabled. The device in which the charge pump is included may be adversely affected by such peak currents.
In response to the peak current issue, charge pumps have been designed such that the pump stages are driven in a staggered fashion to avoid concurrent booting of each pump stage.
FIG. 1
b
illustrates an example of such a charge pump circuit. An oscillator provides an oscillating signal OSC to the first pump stage. The OSC signal is delayed through a first delay circuit before being applied to a second pump stage. Similarly, a third pump stage receives a more delayed OSC signal than a second pump stage. The remaining pump stages, that is, the fourth through sixth pump stages, receive a continually more delayed OSC signal. As a result, each of the pump stages is booted at a different time to avoid creating a severe current load when the charge pump is enabled. A problem, however, with the previously described charge pump circuit is that once a OSC signal is provided to the first pump stage, the other five remaining pump stages will necessarily be booted as well, regardless of whether all six of the pump stages need to be booted to provide a sufficient boosted voltage level. That is, the OSC signal will necessarily propagate through the plurality of delay circuits once the OSC signal is provided. In essence, the power consumed in unnecessarily booting the extraneous pump stages is wasted, thus introducing considerable inefficiencies.
The charge pump circuit illustrated in
FIG. 1
b
has been modified to avoid the unnecessary booting of pump stages by including latches that can be used to halt the propagation of an OSC signal through the chain of delay circuits where less than all of the pump stages need to be booted. The transmission of the OSC signal through the latches is typically under the control of the voltage regulator, which determines how many pump stages should be booted to provide a sufficient boosted voltage. Where less than all of the pump stages are needed, the latch following the last of the necessary pump stages latches the propagating OSC signal and prevents the OSC from further progressing through the chain of delay circuits. Thus, the pump stages downstream of the latch will not be booted.
Although the inclusion of latches in the charge pump is an improvement over the charge pump circuit illustrated in
FIG. 1
b
, inefficiencies are nevertheless still present. In particular, when the charge pump is activated, the first pump stage is always the first to be booted, regardless of where in the sequence of booting the pump stages the oscillator is halted. A situation that illustrates the inefficiencies is as follows. All of the pump stages of the charge pump are being booted by a continuous OSC signal until a sufficient boosted voltage VCCP level is achieved, at which time the voltage regulator halts the oscillator from further providing the OSC signal. At a subsequent time, the voltage regulator restarts the oscillator and boots only the first three pump stages to restore a diminishing VCCP level. After the three pump stages are booted, the oscillator is once again halted. Shortly thereafter, the VCCP level decreases enough to require continuous booting of all of the pump stages. The voltage regulator restarts the oscillator and allows the OSC signal to propagate from the first pump stage through the chain of delay circuits to the sixth pump stage.
In the previous scenario, inefficiency of the charge pump circuit results from the stored charge of the fourth through sixth pump stages being wasted because activation of the charge pump always begins from the first pump stage. More specifically, when the oscillator is first halted, all of the pump stages have been booted and have charge stored on the respective boot nodes. Following the second time the oscillator is halted, only the first three pump stages have been booted, which allows the charge on the boot nodes of the fourth through sixth pump stages to discharge. When the charge pump is restarted again, all of the pump stages are booted in sequence again starting with the first pump stage and progressing through to the sixth pump stage, although the first through third pump stages were most recently booted. While the first through third pump stages are being booted, the charge on the fourth through sixth pump stages continue to discharge until the OSC signal propagates through to chain of delay circuits. A more efficient approach would have been to take advantage of the charge on the boot nodes of the fourth through sixth pump stages before allowing it to discharge rather than restarting the charge pump from the first pump stage.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series. Each of the shift register stages has a control terminal for receiving the oscillating signal and further has input and output terminals. The output of the last shift register stage is coupled to the input of the first shift register stage of the plurality. The shift register stages shift a latched logic state from the input terminal to the output terminal in response to the oscillating signal. The apparatus further includes a duty cycle correcting circuit having input terminals coupled to the output terminals of the shift register stages as well as output terminals at which the plurality of output signals are provided. The duty cycle correcting circuit generates each of the output sig
Butler Hal W.
Merritt Todd A.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Tan T.
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