Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By pulse width or spacing
Reexamination Certificate
1999-07-20
2001-04-24
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By pulse width or spacing
C327S551000, C327S036000, C327S261000, C327S263000, C327S267000
Reexamination Certificate
active
06222393
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal generation circuit. More specifically, a circuit for generating a pulse signal in response to an input signal.
2. Background
Self-timed circuits require a mechanism for internally generating a pulse signal. Often, stringent timings specifications are required by the self-timed circuits. The required pulse may have a specific active pulse width as well as a specific inactive pulse width.
Conventional pulse generation circuits, such as a one-shot circuit, cannot guarantee a specific pulse width. A typical one-shot circuit receives an external clock signal and generates an output pulse of a fixed width provided that the input signal pulse width is greater than the required output pulse width. However, if the input pulse width is less than the required output pulse width, then the output pulse width will be equal to the input pulse width. Clock signal variations may be caused by a variety of factors external to the one-shot circuit itself. When utilizing this type of one-shot circuit, designers must consider potential variations in the external clock signal and design the circuits receiving the one-shot output signal accordingly. Designing with this type of one-shot circuit may require the use of a larger range of timing signal specifications to allow for variations in the external clock signal.
A known one-shot circuit is illustrated in FIG.
1
A. An input line, providing a signal A, is connected to a logic AND gate
14
and a first inverter
10
. The output of inverter
10
is connected to a second inverter
11
, having an output connected to a third inverter
12
. The third inverter has an output connected to AND gate
14
. The one-shot circuit provides an output signal C from the AND gate.
FIG. 1B
is a timing diagram for the one-shot circuit illustrated in FIG.
1
A. This timing diagram represents the situation when the pulse width of signal A is greater than the desired pulse width of output signal C. The rising edge of input signal A generates the rising edge of output signal C after a specific time delay caused by the propagation delay through AND gate
14
. Signal B is inverted and delayed from signal A by inverters
10
,
11
, and
12
. The falling edge of signal B generates the falling edge of output signal C, after the propagation delay of AND gate
14
. Thus, the pulse width of signal C is determined by the propagation delay through inverters
10
-
12
.
FIG. 1C
is another timing diagram for the one-shot circuit illustrated in FIG.
1
A. This timing diagram represents the situation when the pulse width of signal A is less than the delay through inverters
10
-
12
. Thus, the pulse width of signal C is determined by the duration of input pulse A, rather than the propagation delay through inverters
10
-
12
.
SUMMARY OF THE INVENTION
The present invention provides a circuit for generating a pulse signal in response to a rising edge of an input signal. The pulse signal has a pulse width determined by components within the circuit itself and does not rely on a falling edge of an external signal to determine the pulse width. Thus, variations in the pulse width of the external signal do not alter the pulse width generated by the inventive circuit. Accordingly, precise timing specifications can be satisfied by utilizing the present invention.
An embodiment of the present invention includes a first logic device to receive the input signal and generate a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the first intermediate signal. A second logic device is coupled to both the first logic device and the delay device and generates a pulse signal output in response to the first intermediate signal.
Another feature of the present invention provides several delay elements coupled together in a series relationship. Each delay element provides a particular propagation delay. Another aspect of the invention provides a programmable delay device for providing several possible propagation delays.
Another feature of the present invention provides a second delay device coupled to the first and second logic devices. The first delay device determines the pulse width of the output pulse and the second delay device determines the time required for the input pulse to be inactive, thereby resetting the circuit for another pulse. The second delay device allows the circuit to ignore any “glitches” on the input and filter any “noise.”
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Landry Gregory J.
Shah Shailesh
Cypress Semiconductor Corporation
Le Dinh T.
Wagner , Murabito & Hao LLP
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