Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-03-08
2003-12-16
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S284000
Reexamination Certificate
active
06664838
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to electrical delay lines and in particular, to an apparatus and method for generating a compensated percent-of-clock period delay signal.
BACKGROUND OF THE INVENTION
Compensated percent-of-clock period delay signals are useful in many applications. As an example, such a delayed data strobe signal (DQS) is useful for capturing read data (DQ) provided along and edge-aligned with the DQS from a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
The benefits of DDR SDRAMs are well known. Simply put, DDR SDRAMs are probably the most straightforward and least costly approach to doubling memory data bandwidth over the single data rate SDRAMs in common use today.
Read data capture at the memory controller, however, can be a significant challenge using DDR SDRAMs. To assist in read data capture, the DDR SDRAM provides one or more bQS that are edge-aligned with corresponding DQ provided by the DDR SDRAM during a read operation. To capture the data, the memory controller internally delays the received DQS to be within a data valid window, and then captures the DQ using the thus delayed DQS.
The optimal delay for DQS is the average location of the center of the data valid window, taking into account the maximum skew between DQS, DQ (DQSQ”) and the reduced data valid window (DV”) realized at the memory controller. DQSQ” in this case is the sum of the nominal skew between any data line and its corresponding DQS at the pins of the DDR SDRAM (DQSQ) plus skew additions that are incurred between the DDR SDRAM and the memory controller. For example, in a system where the memory controller is on a separate chip than the DDR SDRAM, such skew additions include board effects between the DDR SDRAM and the chip, and internal routing within the chip. Likewise, DV” in this case is the nominal DDR SDRAM data valid window at the pins of the DDR SDRAM (DV)reduced by the skew additions.
A percent-of-clock period delay is only one possible approach for implementing the DQS delay for read data capture. Other approaches include using a predetermined absolute delay value or a selectable delay. Each of these implementations, however, is susceptible to process, voltage and temperature variations that may significantly alter the value of their delay line. Such variations may destroy the limited timing budget available for read data capture. Thus, most systems could benefit
from a delay implementation that addresses one or more of these error-producing variations.
Delay locked loops (DLLs) have been proposed to compensate for at least reference voltage and temperature variations in the predetermined absolute delay value and selectable delay implementations. A DLL locked to the clock is also thought to be required in a percent-of-clock period delay implementation. However, multiple clock periods are generally required for the DLL to “lock” in these implementations, thereby objectionably adding to the effective read access time in short burst read data captures.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an apparatus and method for generating a compensated percent-of-clock period delayed signal that does not require a DLL.
Another object is to provide an apparatus and method for generating a compensated percent-of-clock period delayed signal that compensates for reference voltage and temperature variations.
Another object is to provide an apparatus and method for generating a compensated percent-of-clock period delayed signal that completes its compensation within one clock period.
Still another object is to provide an apparatus and method for generating a compensated percent-of-clock period delayed signal that is cost effective and simple to implement.
These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is an apparatus for generating a compensated percent-of-clock period delayed signal. The apparatus includes a first circuit that generates an output that is indicative of a number of a first plurality of serially coupled delay elements. Individual of such first plurality of serially coupled delay elements have substantially a first delay value. Together, they provide a combined delay related to a period of a clock signal. The apparatus also includes a second circuit that is coupled to the first circuit. The second circuit generates a delayed signal by passing a signal to be delayed through a second plurality of serially coupled delay elements. Individual of such second plurality of serially coupled delay elements have substantially a second delay value. Together, they are related in number to the number of the first plurality of serially coupled delay elements.
Another aspect is a method for generating a compensated percent-of-clock period delayed signal, comprising: determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock signal; and generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, wherein the second number is determined from the first number and the delayed signal is delayed from the signal by a percentage of the period of the clock signal according to values of the first number, the second number, the first delay elements, and the second delay elements.
Still another aspect is an apparatus for generating a compensated percent-of-clock period delayed signal. The apparatus includes a first delay tree that is sensitive to reference voltage and temperature variations. The first delay tree has branches that receive and delay by varying amounts, a clock signal that is relatively insensitive to the reference voltage and temperature variations as compared to the first delay tree. The apparatus also includes a processing circuit that captures outputs of the first delay tree in response to the clock signal so as to indicate a first set of branches of the first delay tree through which the clock signal has passed and a second set of branches of the first delay tree through which the clock signal has not passed during a period of the clock signal. The apparatus further includes a second delay tree similarly sensitive to the reference voltage and temperature variations as compared to the first delay tree. The second delay tree also has branches that receive and delay by varying amounts a signal to be delayed. The apparatus also includes a selection circuit that selects an output of one of the branches of the second delay tree to provide a delayed signal compensated for the reference voltage and temperature variations according to information of the captured outputs of the first delay tree.
REFERENCES:
patent: 5561692 (1996-10-01), Maitland et al.
patent: 6194937 (2001-02-01), Minami
patent: 6288574 (2001-09-01), Neary
patent: 6313621 (2001-11-01), Zwack
patent: 6313676 (2001-11-01), Abe et al.
Ryan, Kevin, “DDR SDRAM Functionality and Controller Read Data Capture,” DesignLine, Micron Technology, Inc., vol. 8, Issue 3, 3Q99.
Callahan Timothy P.
Cox Cassandra
Integrated Device Technology Inc.
Okumoto, Esq. Victor H.
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