Static information storage and retrieval – Addressing – Sync/clocking
Utility Patent
1998-05-20
2001-01-02
Nelms, David (Department: 2819)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S189050
Utility Patent
active
06169704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to semiconductor devices, such as semiconductor memory devices, and, more specifically, to devices and methods for generating a clock within a semiconductor device, such as an internal clock for a Synchronous Dynamic Random Access Memory (SDRAM).
2. State of the Art
Most conventional DRAMs have an asynchronous timing relationship with the electronic components they interact with. The recently popular SDRAMs, on the other hand, are generally synchronized with the electronic components they interact with through the use of one or more shared clocks.
Within a typical SDRAM, shared clocks are used to latch signals in and out of the SDRAM and to time a wide variety of other internal operations. Since signals appearing at the inputs of the typical SDRAM take some time to rise or fall to their maximum or minimum potential, the shared clocks used by the SDRAM typically have to be delayed within the SDRAM before being used to latch input signals. This delay time is selected to allow the input signals sufficient time to stabilize at the inputs to the SDRAM.
The circuit used to delay a shared clock within an SDRAM is typically referred to as a “clock generator” or simply as a “generator.” One such prior art generator
10
is shown in FIG.
1
. As shown, the generator
10
includes an inverting input buffer
12
, an inverting latch
14
, a clock rising edge path
16
, a clock falling edge path
18
, and a switching circuit
29
.
In a steady state of the generator
10
, a low external clock XCLK provided to an SDRAM (not shown) causes the input buffer
12
to output a high. At the same time, an inverter
20
makes the inputs to a NAND gate
22
complementary, which causes the NAND gate
22
to output a high. The highs from the input buffer
12
and the NAND gate
22
cause another NAND gate
24
to output a low which, in turn, causes an inverter
26
to output a high, an inverter
28
to output a low, a NAND gate
30
to output a high, and an inverter
32
to output a low SDRAM internal clock CLKA. The low output from the NAND gate
24
also causes the inverter
20
to output a high which, in turn, causes a NOR gate
34
to output a low, an inverter
36
to output a high, an inverter
38
to output a low, an inverter
40
to output a high, and an inverter
42
to output a low.
In general, when the external clock XCLK pulses high, the rising edge path
16
responds by causing the switching circuit
29
to pulse the internal clock CLKA high after a brief delay, and the falling edge path
18
responds by later causing the switching circuit
29
to pull the internal clock CLKA low after a slightly longer delay. This provides a clock pulse on the internal clock CLKA for each pulse on the external clock XCLK.
More specifically, the input buffer
12
outputs a low in response to the high external clock XCLK which, in turn, causes the NAND gate
24
to output a high, the inverter
26
to output a low, and the inverter
28
to output a high. The highs from the inverters
28
and
40
then cause the NAND gate
30
to output a low, which causes the inverter
32
to pulse the SDRAM internal clock CLKA high as described above. The delay time (&Dgr;t
r
) between the rising edge of the external clock XCLK and the rising edge of the SDRAM internal clock, CLKA, caused by delays associated with the input buffer
12
, the latch
14
, the clock rising edge path
16
, and the switching circuit
29
, gives input signals provided to the SDRAM time to develop at the inputs of the SDRAM before being latched into the SDRAM by the SDRAM internal clock CLKA.
Also, while the switching circuit
29
is pulsing the internal clock CLKA high, the high output by the NAND gate
24
causes the inverter
20
to output a low which, after propagating through several delay elements
44
, causes the NOR gate
34
to output a high, the inverter
36
to output a low, the inverter
38
to output a high, the inverter
40
to output a low, and the inverter
42
to output a high. The low from the inverter
40
causes the NAND gate
30
to output a high which, in turn, causes the inverter
32
to pull the internal clock CLKA low. At the same time, the high output by the inverter
42
activates a pull-down NMOS transistor
46
which helps the inverter
32
pull the internal clock CLKA low. The delay time (&Dgr;t
f
) associated with the input buffer
12
, the latch
14
, the falling edge path
18
, and the switching circuit
29
is greater than the delay time (&Dgr;t
r
) associated with the rising edge path
16
, which allows the falling edge path
18
to pull the internal clock CLKA low after the rising edge path
16
pulses the internal clock CLKA high, thereby creating a delayed pulse on the internal clock CLKA for each pulse on the external clock XCLK.
Unfortunately, under certain extreme temperature and/or supply voltage conditions, the delay &Dgr;t
f
associated with the falling edge path
18
can decrease just enough, and the delay &Dgr;t
r
associated with the rising edge path
16
can increase just enough, that the falling edge path
18
pulls the internal clock CLKA low too soon after the rising edge path
16
pulses the internal clock CLKA high, or even before the rising edge path
16
pulses the internal clock CLKA high, in response to the external clock XCLK pulsing high. As a result, the generator
10
outputs an unrecognizable internal clock CLKA. This occurs because process variations between the various components that make up the two paths
16
and
18
can cause these paths
16
and
18
to respond differently to temperature and supply voltage variations.
Therefore, there is a need in the art for an improved clock generator that produces a recognizable internal clock even under such extreme temperature and supply voltage variations.
SUMMARY OF THE INVENTION
To overcome the problem of generating a stable and recognizable internal clock signal under extreme operating conditions of temperature and/or supply voltage, the method and apparatus of the present invention utilizes a latch, a switching circuit and a feedback path, where the switching circuit is interposed between the latch and the feedback path.
In the leading edge phase of the input clock signal, the latch element takes the leading edge of the input clock signal and presents that signal on its output. The switching circuit drives the output clock signal leading edge based on the latch output. The feedback path couples the output clock signal back to the latch and the switching circuit, which in turn, drive the trailing edge of the output clock signal. The trailing edge of the output clock signal will not occur unless the leading edge of the output signal has occurred first.
During the trailing edge phase of the input clock signal, the latch and the switching circuit are returned to their initial states. Once the initial states have been reset, the clock generator circuit is ready for the next input clock signal.
The inventive clock generator thus provides an internal clock pulse that corresponds to each pulse on an external clock. The internal clock pulse is recognizable under even the most extreme temperature and/or supply voltage variations because the clock generator does not drive the internal clock low until it first senses, through feedback, that the internal clock has been driven high.
The inventive clock generator circuit is suitable for memory circuits, pulse generators, Address Transition Detection circuitry, and any other circuit or electronic system in which a stable output pulse is to be generated from an input pulse signal. The inventive clock generator can be fabricated using conventional techniques on any suitable substrate. These and other embodiments and advantages of the invention will be readily understood by reading the following detailed description in conjunction with the accompanying figures of the drawings.
REFERENCES:
patent: 4727519 (1988-02-01), Morton et al.
patent: 4761568 (1988-08-01), Stronski
patent: 5204555 (1993-04-01), Graham et al.
patent: 52727
Britt Trask
Le Thong
Micro)n Technology, Inc.
Nelms David
LandOfFree
Apparatus and method for generating a clock within a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for generating a clock within a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for generating a clock within a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2450044