Apparatus and method for forcing hardware errors via scan

Details Apparatus and method for forcing hardware errors via scan Apparatus and method for forcing hardware errors via scan

1992-12-18

1995-09-19

Voeltz, Emanuel T.

Excavating

371 221, G01R 3128

Patent

active

054523095

ABSTRACT:
An apparatus and method for forcing stuck-at and transient errors at sequential and combinational logic and signal lines in a large scale data processing system. Error forcing is achieved by including a scan-in gate with error input and address lines for each scan point to be tested. A fault signal of adjustable duration is generated and combined in a unique fashion to an existing scan-in signal to permit either stuck-at or transient errors to be forced.

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patent: 5012180 (1991-04-01), Dalrymple et al.
patent: 5115191 (1992-05-01), Yoshimori
patent: 5260649 (1993-11-01), Parker et al.
patent: 5285153 (1994-02-01), Ahanin et al.
patent: 5303246 (1994-04-01), Anderson et al.

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