Apparatus and method for floating point normalization prediction

Details Apparatus and method for floating point normalization prediction Apparatus and method for floating point normalization prediction

1988-04-01

1990-05-01

Malzahn, David H.

Boots, shoes, and leggings

36471504, G06F 750

Patent

active

049224468

ABSTRACT:
The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision floating point adder/subtractor, a priority encoder that determines the position of the most significant non-zero bit to generate the normalization amount and preround logic which pre-shifts a rounding bit in the opposite direction of normalization. The method and apparatus operate in parallel with a full precision floating point adder to eliminate the need for a full-precision floating point normalization calculation and rounding computation in most circumstances. The normalization amount for successful low-precision floating-point addition/subtraction is calculated by the time the full-precision floating-point addition/subtraction stage occurs. Moreover, the pre-round logic supplies a carry bit to the full-precision adder/subtractor thus saving the time associated with a full-precision rounding bit addition. Thus, this low-precision floating-point addition/subtraction technique results in a significant enhancement of performance in floating-point addition/subtraction.

REFERENCES:
patent: 4758974 (1988-07-01), Fields et al.
patent: 4779220 (1988-10-01), Nukiyama
"Pipeline Control in Pre-Norm Logic", IBM Tech. Disclosure Bulletin, vol. 30, No. 1, Jun. 1987, pp. 79-86.

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