Computer graphics processing and selective visual display system – Display peripheral interface input device
Patent
1996-10-11
1999-10-05
Chin, Wellington
Computer graphics processing and selective visual display system
Display peripheral interface input device
345502, 345519, 345112, 345113, G09G 502
Patent
active
059631929
ABSTRACT:
A single-chip video-graphics controller includes a novel circuit for eliminating full line buffers when reducing line-to-line flicker in a display image of non-interlaced data on an interlaced color display device such as an NTSC or PAL television projector. The flicker reduction circuit uses a pair of memory access agents for concurrently fetching even and odd interlace frames of the display image. Corresponding color pixels of the two frames are averaged on-the-fly, and the averaged output is converted to analog RGB output signals for driving the display device. The elimination of the full line buffers results in a savings of approximately 30,000 transistors per buffer and a corresponding reduction in operating power. A specific embodiment of the controller includes a vertical stretching circuit used to adjust the number of vertical lines corresponding to the display image permitting the vertical reformatting of any display image.
REFERENCES:
patent: 4393394 (1983-07-01), McCoy
patent: 5473342 (1995-12-01), Tse et al.
patent: 5510843 (1996-04-01), Keene et al.
Product Data Book, 86CM65 Aurora64V+ Dual Display Accelerator, Section 11: Flat Panel Interface, S3 Incorporated, Santa Clara, California (Jul. 1996) pp. 1-14.
Chang Richard L.C.
Wong Raymond M.Y.
Chin Wellington
Ferguson Keith
Silicon Motion Inc.
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