Apparatus and method for flexible control of digital signal proc

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364726, 364736, 364224, 364243, 3642457, 3642715, 3642741, 3642816, G06F 15332, G06F 7544, G06F 1316

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050290797

ABSTRACT:
A control apparatus for use with a digital signal processing device and associated memory units is described. The control apparatus determines, along with the electrical configuration of the digital signal processing device and associated memory units, the application of members of a signal array to be processed and the removal of the members of a processed signal array from the digital signal processing device. The control apparatus controls the location of data exchanged between the digital signal processing device and the associated memory units. The control apparatus permits the digital signal processing device and associated memory units to operate in a normal mode where a predetermined processing operation is performed on the members of a signal array, a recursive mode where a series of operations are performed on a signal array by a single digital signal processing unit, and a sequential mode where a series of processing operations are performed on a signal array using a by plurality of digital signal processing units coupled in a series arrangement. The control apparatus has provision for automatic accommodation of predetermined latency in the signal member path, resulting from pipelined computation and from pipelined memory accesses, as well as accommodating preselected signal array sizes and preselected signal array overlap.

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David Quong and Robert Perlman, Electronic Design, vol. 32, Jul., 1984, No. 14, "One-Chip Sequencer Shapes up Addressing For Large FFTs", pp. 159-164, 166, 168.
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Zoran Data Sheet for ZR34161 Vector Signal Processor, Jul. 30, 1986, pp. 7-18.
Supplemental Data Sheet for Zoran Data Sheet for 2R 34161 Vector Signal Processor, pp. 20-26.

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