Electrical computers and digital processing systems: processing – Instruction fetching – Of multiple instructions simultaneously
Reexamination Certificate
1999-02-12
2002-04-02
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Of multiple instructions simultaneously
C712S029000, C712S214000, C712S211000, C711S125000, C711S173000, C711S129000, C711S209000
Reexamination Certificate
active
06367002
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus that is, to an apparatus and a method for retrieving instructions for a program-controlled unit, having an instruction queue for furnishing instruction data retrieved previously from a program memory.
The program-controlled unit to be supplied with instruction data by the apparatus or the method is for instance a microprocessor, microcontroller, or the like.
The instruction queue is a component of the instruction retrieval device of the program-controlled unit. It is configured for buffer storage of many instruction data representing instructions and outputting them as needed, that is, when the execution of the applicable instruction is incipient, to an instruction execution unit of the program-controlled unit.
The instruction data written into the instruction queue are read out from the program memory provided either inside or outside the program-controlled unit. Fetching the instruction data from the program memory and writing them into the instruction queue are done without interruption, and as a rule independently of the rhythm at which the program-controlled unit, or more specifically its instruction execution unit, executes the instructions. The process is interrupted only if any instructions still to be executed would thereby be overwritten in the instruction queue.
It proves to be advantageous to furnish instruction data representing instructions in the instruction queue, because the instruction queue permits very rapid access to the instruction data, and thus the instruction execution unit of the program controlled unit thus seldom or never needs to wait for very long for the instruction data representing the next instruction.
However, this is true only if and as long as the instructions are executed in the order in which they are stored in the program memory and thus also in the instruction queue, which in turn is true only if and as long as no jump instructions, task changes, interrupts, and so forth occur in the program execution. In the case of the non-address-sequential program execution occurring in such cases, the instruction data already furnished in the instruction queue can no longer be used, because after all in any case they derive randomly from the address at which the instruction, to be executed after a jump or the like, is to be retrieved. Such events are usually reacted to in the form of a so-called queue flush, the result of which is that the data furnished in the instruction queue are discarded, and the readout of instruction data from the program memory (and their writing into the instruction queue) are continued from the target address of the jump onward.
In such situations, a pause occurs in the program execution, because the instruction data representing the instruction to be executed after a jump or the like must after all first then be retrieved from the normally comparatively low-speed program memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an apparatus and a method for fetching instructions for a program-controlled unit that overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the incidence of pauses in program execution is reduced to a minimum.
With the foregoing and other objects in view there is provided, in accordance with the invention, an apparatus for retrieving instructions for a program-controlled unit having a program memory, including: an instruction queue unit having a plurality of defined points for storing and furnishing instruction data retrieved beforehand from the program memory, the plurality of defined points within the instruction queue unit starting up selectively if the instruction data are written into the instruction queue unit and/or the instruction data are read out of the instruction queue unit.
Accordingly, it is provided that the instruction queue is configured such that, when instruction data are written into the instruction queue and/or when instruction data are read out of the instruction queue, a plurality of defined points within the instruction queue are made to start up selectively, and that the instruction queue is configured such that, when instruction data are written into the instruction queue and/or when instruction data are read out of the instruction queue, one of a plurality of defined points within the instruction queue is started up selectively in response to certain events.
The selective startability of a plurality of certain points within the instruction queue proves to be advantageous in two respects. First, because a plurality of instruction sequences can thus be stored in the instruction queue simultaneously but independently of one another, and second, because the instruction queue can thus also be used as an instruction cache.
Both of these factors contribute to the capability that the instruction data, needed by the instruction execution unit of the program-controlled unit, at the moment when they are needed are always or virtually always already or still available in the instruction queue and can be taken over from there immediately, that is, without waiting.
As a result, the incidence of pauses in program execution can be reduced to a minimum.
In accordance with an added feature of the invention, the instruction queue unit has an instruction queue buffer subdivided into multiple regions.
In accordance with an additional feature of the invention, each of the multiple regions of the instruction queue buffer stores the instruction data representing a plurality of instructions from the program memory.
In accordance with another feature of the invention, the instruction queue buffer is used entirely or partially as an instruction cache.
In accordance with a further added feature of the invention, the instruction queue unit has a predecode unit and the instruction data read out of the program memory are checked in the predecode unit to determine if the instruction data represent instructions whose execution can result in an occurrence of a non-address-sequential program sequence.
With the foregoing and other objects in view there is also provided, in accordance with the invention, an improved method for retrieving instructions for a program-controlled unit having an instruction queue unit for furnishing instruction data retrieved beforehand from a program memory, the improvement which includes: responding to certain events by starting up selectively one of a plurality of defined points within the instruction queue unit if at least one of the instruction data are written into the instruction queue unit and the instruction data are read out of the instruction queue unit.
In accordance with an added feature of the invention there is the step of predicting with the predecode unit on detecting the instruction whose execution can cause the occurrence of the non-address-sequential program sequence, an address from which a program execution should be continued in an event of the non-address-sequential program sequence occurring.
In accordance with an additional feature of the invention, there is the step of starting a reading out of further instruction data from the program memory that are to be executed if the instruction data capable of causing the non-address-sequential program sequence actually causes the occurrence of the non-address-sequential program sequence upon execution of the instruction data before the instruction data are executed after detecting the instruction data whose execution can result in the occurrence of the non-address-sequential program sequence.
In accordance with another feature of the invention, there is the step of writing in a new region of the instruction queue buffer the further instruction data read out of the program memory that are to be executed in the event of the occurrence of the non-address-sequential program sequence.
In accordance with a further added feature of the invention, there is the step of reading and storing a certain minimum number of additional instru
Pan Daniel H.
Siemens Aktiengesellschaft
LandOfFree
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