Optics: measuring and testing – Position or displacement
Reexamination Certificate
1999-04-15
2003-09-23
Font, Frank G. (Department: 2877)
Optics: measuring and testing
Position or displacement
C356S615000, C356S630000
Reexamination Certificate
active
06624897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, in particular, to a method and apparatus for improving the alignment of pattern masks to semiconductor wafers.
2. Description of the Related Art
Trends toward smaller critical dimensions in semiconductor processing have caused an exponential increase in the precision with which fabrication processes must be performed by the semiconductor device manufacturer. Semiconductor based integrated circuits are typically manufactured through the formation of a set of layers on a wafer containing many integrated circuit areas which will later be separated into individual dies. Very thin layers of material are deposited one on top of the other in patterns to form integrated circuit components. One technique of deposition and patterning is photolithography wherein a material layer is first coated with a light-sensitive photoresist. The photoresist is exposed through a pattern mask of a desired circuit pattern. The exposed photoresist is developed to remove, depending upon the type of photoresist used, either the exposed or unexposed resist. Etching and/or deposition processes are then used to create the desired circuit within the pattern created.
It is imperative to the process of photolithography that the pattern mask be precisely aligned on a wafer during processing. The overlay of the mask, the measure of how accurately the pattern mask was aligned, will often determine whether the wafer will be functional or must be discarded. Because each wafer must undergo numerous photolithography processing steps, the alignment of each pattern mask, especially the last ones used, is dependant upon the correct alignment of earlier masks. Poor overlay destroys the intended electrical properties of a circuit device on a wafer.
Prior art alignment approaches have used numerous methods for aligning a pattern mask to a wafer. One such method is the formation or use of reflective targets within the material layers deposited on a wafer prior to the alignment of the pattern mask. The targets, such as vertical scores or pronounced feature edges between two material layers, are illuminated by a light source and the resulting contrast created by the target is used to visually align the pattern mask. However, in wafers in which, for example, an oxide layer has been deposited in a silicon substrate such that the surfaces of the oxide and the substrate are even, the system fails because no physically distinct feature edge exists. In addition, the detection of minute feature edges is further complicated after numerous material layers have been deposited on top of the feature edge which must be detected. Visibly opaque materials and variations in colors between material layers will also degrade the performance of such a system.
U.S. Pat. No. 5,343,292 (Brueck, et al.), U.S. Pat. No. 4,991,962 (Kantilal Jain), and U.S. Pat. No. 4,631,416 (William Trutna Jr.) use interferometry to establish a phase shift within reflected light to create target patterns for alignment of a mask. The phase shift of a wide light beam as it encounters a feature edge, the boundary between a substrate and a material layer which has been deposited into a substrate, can be detected if that light beam is only reflected by the substrate material. A diffraction grating pattern will emerge in the reflected light and this can be used to align pattern masks. However, the existence of material layers above the edge to be detected dilutes the precision of this measurement technique by weakening the interference pattern. In addition, interferometry systems which rely upon a physically distinct edge are imprecise when two materials have equivalent heights at the material boundary edge.
None of the described methods allows for in-line identification of feature edges to allow accurate and repeatable registration of pattern masks within the increasingly reduced critical dimensions made possible by recent advancements in wafer fabrication.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus that is able to overcome some of the problems attendant the alignment of pattern masks in semiconductor fabrication of small critical dimension devices.
The above and other features and advantages of the invention are achieved by providing an apparatus for the detection of a layer step or feature edge of a die or wafer using spectroscopic reflectance to detect a change in the reflectance spectral response at the step or edge. The detection of a feature edge may be used, for example, to align a pattern mask for photolithography processing of the wafer.
In integrated circuit fabrication, a wafer is subjected to wafer fabrication processes to produce a number of individual layers on a semiconductor substrate. During processing, a reflectometer emits electromagnetic radiation having a predetermined wavelength range. The intensity or reflectivity of the radiation which is reflected from the wafer is monitored for changes which signal the detection of a feature edge within or on the wafer. The use of a specific range of electromagnetic wavelengths with the reflectometer allows the apparatus to detect feature edges covered by material which is visibly opaque, that is the material is opaque or semi-opaque in the visible wavelength range of 400 nm to 700 nm. After a feature edge has been detected, the apparatus may be used to accurately align a pattern mask according to the data collected by the reflectometer.
The above and other advantages and features of the present invention will be better understood from the following detailed description of the preferred embodiment which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 4631416 (1986-12-01), Trutna, Jr.
patent: 4991962 (1991-02-01), Jain
patent: 5343292 (1994-08-01), Brueck et al.
patent: 5726074 (1998-03-01), Yabe
patent: 5978074 (1999-11-01), Opsal et al.
patent: 6278519 (2001-08-01), Rosencwaig et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Punnoose Roy M.
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