Boots – shoes – and leggings
Patent
1985-06-13
1988-03-29
Zache, Raulfe B.
Boots, shoes, and leggings
365189, G06F 1200
Patent
active
047348550
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to processing data or information, and more particularly to storage thereof, when said storage has to be performed with a high degree of security.
In numerous applications, and in particular those related to distributed computing, it is desirable to have stable memories available.
A stable memory is a data storage device which possesses the following properties: firstly, the physical storage of information is stable, i.e. information does not tend to disappear with passage of time; and, secondly, the operation of writing is capable of being made "atomic", i.e. once information has been presented for writing, onc can be certain that the information is correctly written or else it is not written at all.
At present, stable memories are made from disks. Although disks do not directly provide stable data storage, they enable such stable storage to be obtained, in particular by conjoint use of two disk units. However, this method of proceeding has drawbacks. The first drawback is that the access time to a disk memory is not short enough for a stable storage unit based on disks to be considered as being a fast memory. The other drawback is that the stable character of the memory is obtained by copying the same information into both disk units. The controlling processor uses its own read/write memory to perform this double copying operation. As a result, if an error occurs in said processor between writing to one of the disks and writing to the other disk, the stable character of information storage is compromised.
SUMMARY OF THE INVENTION
The present invention solves these drawbacks, by providing firstly a memory (or data storage) device having fast access and capable of offering stable storage, and secondly by avoiding as much as possible any use of the processor's read/write memory for copying information into two different sections of memory.
The proposed data storage apparatus comprises, in combination: and which are provided with selective write or read controls; and banks and for subsequently responding to the insertion of one of the keys accompanied by a write or a read request by selectively authorizing writing or reading in a manner which is applicable to the single memory bank defined by the said key, said authorization being destroyed after any memory bank has been addressed or after any new key has been inserted, thereby enabling each of the n memory banks to be used independently and successively by different processes without any risk of uncontrolled access.
In an advantageous embodiment, the key access means comprise: function of its index k, of receiving or of delivering at the output from the table a byte having not more than one bit which is different from the others; and outlets from the access table, said registers enabling one additional register designated by the different bit of the byte defined by the current index, each register possessing at least three states, including a rest or no access entitlement state, together with two access entitlement states for writing and reading respectively, which states can only be taken when the register is enabled.
With each memory bank being associated with a respective one of the registers in such a manner as to respond to external addressing only if a write or a read access entitlement has been noted in the associated register.
Preferably, the outlets from the access entitlement registers are applied to two multiplexers respectively for writing and for reading addresses in accordance with the number of the memory bank being addressed, write or read authorization being given to the memory banks by the outlet from the write multiplexer or from the read multiplexer, as the case may be.
The invention also provides a method of transferring data between a processor and a data storage device as defined above. The processor is deemed to be required to run a plurality of independent processes. The method comprises the following operations:
(a) on each request for new memory from a process, allocati
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Banatre Jean-Pierre A. F. J.
Banatre Michel P. P. A.
Decouty Bertrand J. G.
Ployette Florimond E. A.
Prunault Yves H.
INRIA-Institut National de Recherche en Informatique et en Autom
Zache Raulfe B.
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