Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-03-03
2004-02-10
Eckert, George (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S613000, C438S108000, C438S455000, C257S782000
Reexamination Certificate
active
06689635
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electrically connecting a integrated circuit or die to a substrate. More particularly it relates to an apparatus and method for face-to-face connection of a die to a substrate with polymer electrodes.
2. Description of Related Art
From its inception the electronics industry has been driven by the demand for improved performance from both electronic components and electronic products. Every aspect of the industry is under constant scrutiny and is pressure to surpass current levels of performance. Electronic components are expected to be ever smaller, faster, lighter, more powerful and more reliable.
The integrated circuit has remained a constant target in the drive for improved performance. In response to industry demands, the integrated circuit or chip has evolved to accommodate ever more numerous electronic functions into increasingly smaller areas.
Miniaturization of computer chips has provided multiple benefits: not only have the chips become smaller and lighter, but the cost of making a chip has decreased and its performance has increased. The shrinking dimensions have reduced the time and distance of electrical signal transmission through the integrated circuit.
In addition to all of the benefits of miniaturization, new challenges and demands are also a consequence of miniaturization. Before the chip is ready to be plugged into an electronic device it must undergo further processing. In this stage of manufacturing the chip is mounted in a sturdy encasement that protects it from a variety of sources of damage and contamination. Other major functions of the encasement or electronic package include providing a path for the electrical current that powers the circuit, remove heat generated by the circuit and allow the routing of signals onto and off of the chip.
Bonding is the first step in packaging the chip. The purpose of bonding is to establish electrical connections between the chip or die and the package conductors, called leads or pins, that connect the chip to a substrate or circuit board. In concert with the shrinking size of integrated circuits their complexity has increased. This presents a problem from the perspective of packaging, because with the increased complexity of the chip there is a need for more metal conductors on the substrate, and less room available for components.
One response to such competing demands has been innovation in the methods of circuit interconnection. One method of bonding or interconnection that has addressed some of the emerging challenges is a method of attaching the active surface of the chip or die facing down, towards the substrate, this is also referred to as flip chip bonding. In face-down bonding the process that cements the die to the substrate also makes the electrical connections between the die and substrate. This face-down connection eliminates the need for long wire leads between the respective bonding pads, thereby providing desirably shorter leads. Face-to-face bonding also accommodates other desirable traits, including greater input/output, smaller device footprints and higher density.
The increasing use of face-down chip bonding has exposed both the strengths and weaknesses of the technique. Some forms of face-down chip bonding or interconnection use metal solder bumps. Some of the problems associated with the use of metal interconnections are heat stresses, from thermal coefficient of expansion mismatches, during fabrication; and the formation of electrically conductive flux between the face-down chip and the substrate. The electrically conductive flux from the melting of metal solder bumps must be removed so that the interconnection will function properly. The flux removal adds an additional and undesirable step to the bonding process.
Kulesza and Estes addressed some of these problems by eliminating the metal solder bumps and using conductive polymers in flip chip interconnections, as disclosed in their U.S. Pat. Nos. 5,074,974, 5,196,371 and 5,237,130.
Their methods teach the formation of a polymer bump on the chip and then contacting the chip to the bonding pad of the substrate. At least one disadvantage of this is requirement of the heating of the substrate or circuit board to accomplish the bonding. Since the board is made of an insulating material it is relatively more difficult and temperamental to heat than the chip, this limits the speed at which the chip can be applied.
There is still a need for methods of face-down interconnection of a chip to a substrate that are simple, reliable and cost effective.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for connection of a die face to a substrate with polymer electrodes, the method comprising forming a plurality of conductive polymer electrodes on the substrate assembly; and elevating the temperature of the die sufficiently to cause electrical and fixed connection of the die to the electrodes upon appropriate contact; and bringing the die face and electrodes into appropriate contact thereby forming the fixed and electrical connection. In other embodiments the electrodes may be formed on the die face rather than the substrate assembly or the electrodes may be formed on both the die face and substrate assembly.
Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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Estes, R.H., “Technology Assessment: PFC Polymer Flip Chip Solderless Bump Process”,Epoxy Technology, Technical Paper: GB-31, pp. 2-9.
Estes, R.H., et al., “Conductive Adhesive Polymer Materials in Flip Chip Applications”,Flip Chip Technologies, Edited by John H. Lau, Chapter 6, 223-267, (1996).
Cobbley Chad
Jiang Tongbi
Díaz José R
Eckert George
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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