Electrical computers and digital processing systems: processing – Architecture based instruction processing – Multiprocessor instruction
Reexamination Certificate
2008-07-01
2008-07-01
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Multiprocessor instruction
C712S213000
Reexamination Certificate
active
10227008
ABSTRACT:
An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in the microprocessor instruction set. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the microprocessor. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies an extended operand size for an operand corresponding to a prescribed operation, where the extended operand size cannot be specified by an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions and performs the prescribed operation using the operand.
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Henry G. Glenn
Hooker Rodney E.
Parks Terry
Huffman James W.
Huffman Richard K.
iP-First, LLC
Pan Daniel
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