Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2004-12-01
2009-06-02
Kindred, Alford W (Department: 2181)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S218000
Reexamination Certificate
active
07543134
ABSTRACT:
An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.
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Henry G. Glenn
Hooker Rodney E.
Parks Terry
Huffman James W.
Huffman Richard K.
IP-First LLC
Kindred Alford W
Moll Jesse R
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