Patent
1997-05-12
1998-07-21
Lall, Parshotam S.
395591, G06F 922
Patent
active
057846073
ABSTRACT:
An apparatus and method for handling exceptions during execution of string instructions is provided. The apparatus includes translate/decode logic which repetitively generates a micro instruction sequence applicable to the particular string operation, and an execution unit for executing the micro instruction sequence. A counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is incremented/decremented each time the sequence is executed. The translate/decode logic continues to generate the micro instruction sequence until receiving a signal from the counter which indicates that all of the string has been operated upon, e.g., if the counter reaches zero. If exceptions occur during the operation of the translate/decode logic generated string instructions, the value of the counter is stored in a temporary register, the string operation is ended as if the counter reached zero, the exception is handled, the value of the counter is restored, and the string operation is resumed where it was interrupted.
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Henry G. Glenn
Parks Terry
Huffman James W.
Integrated Device Technology Inc.
Lall Parshotam S.
Vu Viet
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