Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-12-14
2002-12-24
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C438S017000
Reexamination Certificate
active
06498502
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention generally relates to the field of electronic devices. More specifically this invention relates to an apparatus and method for evaluating semiconductor structures and devices.
BACKGROUND OF THE INVENTION
Advancements in the semiconductor industry have converged on developing submicron geometric devices for microelectronic circuits. Semiconductor fabrication processes, in their infancy, were sometimes plagued with fatal defectivity that inhibited the production of integrated circuits. As semiconductor fabrication processes became more advanced, the level and occurrence of defects in semiconductor devices have decreased. However, the reduction of semiconductor geometries to submicron levels has manifested inherent defect modes which may impact the performance of resulting semiconductor devices.
Silicon wafers provide a common substrate used to fabricate multiple semiconductor devices. As geometries for semiconductor devices are reduced, the inherent characteristics of the device's materials such as silicon become a significant factor. Structural defects are one of the inherent problems facing the advancement of submicron semiconductor devices. Some structural defects negatively impact device performance and may effect, for example, leakage currents, carrier lifetimes, and gate oxide integrity.
There are several different classifications of structural and process defects that can occur in semiconductor devices. One defect that occurs in semiconductor processing is an area defect called grain boundaries. Grain boundaries occur when certain planes of atoms terminate from one process layer and a subsequent layer fills-in the region between the two grains. For example, when an oxide layer is deposed onto silicon, the atoms in the region of the boundary are displaced from their normal position. This displacement is generally confined to a region very close to the grain boundary. Thus, a semiconductor device having multiple process layers typically has several different material interfaces. As a result, any two layers may have an angle of misorientation that occurs during a single process. As grains of the layers form an intersection, certain rows of atoms within each layer's lattice structure may not line up and extend their full length at the junction. This causes a dislocation between the two layers resulting in a grain boundary.
Another defect that occurs in semiconductors is caused by voids in the lattice material due to precipitates of extrinsic or intrinsic point defects. Precipitates are a complicated defect mode that include the formation of an intermediate crystal structure that later transforms into a final structure. The initially formed precipitate particle is called a nuclei and the transformation process is called a nucleation process. The nucleation process can occur in two ways, heterogeneous nucleation that occurs at a crystalline defect such as a dislocation, a grain boundary, or an impurity. The second process is homogenous nucleation, a random composition of the nuclei. In general, during a nucleation process, the more rapid diffusion of the semiconductor material, the more quickly precipitation occurs.
A bulk defect that occurs in one silicon crystal layer can be the cause of other crystalline defects as additional layers are grown. For example, the growth of oxygen precipitates in silicon occurs by the reaction of oxygen with silicon at the precipitate surface to form silicon dioxide. The volume change from silicon to silicon dioxide is almost two to one with silicon dioxide being the larger. Consequently, the lattice surrounding the silicon dioxide precipitate is subject to large compressions placing undue stress on the lattice and junction regions which can lead to a bulk defect within the lattice structure.
Therefore, as semiconductor device geometry's become smaller, evaluating the effects of both intrinsic and extrinsic defects are critical in optimizing the performance of semiconductor devices and structures and associated fabrication processes.
SUMMARY OF THE INVENTION
In accordance with the present invention, an apparatus and methods are provided which substantially eliminates or reduces disadvantages and problems associated with prior device evaluation methods and apparatuses.
The present invention discloses a method for evaluating at least one selected electrical property of a semiconductor device in relation to a selected geometric dimension of the semiconductor device. The method includes forming a plurality of semiconductor devices on a substrate, the devices having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device. The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.
More specifically, the method further includes measuring a topography of the semiconductor device using a scanning probe microscopy based technique.
More specifically, the method further includes measuring the topography in a region proximal to the measured electrical property.
The present invention also provides a method for evaluating a semiconductor device. The method includes providing the semiconductor device, measuring a first characteristic of the device using a first--scanning probe microscopy technique, and measuring an electrical property of the device using a second scanning probe microscopy technique. The method further includes determining variations in the semiconductor device based upon the measured first characteristic and the measured electrical property wherein the first characteristic and the electrical property are measured in a proximal region to one another.
More specifically, the method includes providing a semiconductor device with a selected geometric dimension of less than one micrometer.
More specifically, the method includes measuring the first characteristic and the electrical property simultaneously.
The present invention further provides a system for evaluating semiconductor devices. The system includes a processor, a storage medium operably coupled to the processor, a scanning probe microscopy device, operably coupled to the processor to evaluate semiconductor devices wherein the scanning probe microscopy includes a probe configured to measure at least one electrical property of the semiconductor device. The system further includes a program of instructions for evaluating a semiconductor device, the program of instructions including at least one instruction configured to measure the at least one electrical property and determining a relationship between the measured electrical property and at least one geometric dimension of the device.
More specifically, the system is configured to include a nanoscopic probe.
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Edwards Henry L.
Moise Theodore S.
Wilk Glen D.
Brady III Wade James
Patel Paresh
Sherry Michael
Telecky , Jr. Frederick J.
Texas Instrument Incorporated
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