Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Utility Patent
1998-07-08
2001-01-02
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S019000, C703S020000, C716S030000, C716S030000
Utility Patent
active
06169968
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to apparatus and method for estimating a performance of an integrated circuit, in which a performance of an integrated circuit such as the area and the operation speed is estimated in the design at a register transfer level.
In accordance with the recent refinement of semiconductor manufacturing processes and the increased scale of integrated circuits, the design of integrated circuits has become more and more complicated, and correction after detailed design has become very difficult. As a result, the design time has been disadvantageously elongated due to iterations in the design.
Therefore, in order to prevent the elongation of the design time due to the iterations in the design, a design method, in which the performance of an integrated circuit is estimated at an early stage of the design, so that problems can be overcome before the detailed design on the basis of the estimation, has become considered to be significant.
As a conventional performance estimation method for an integrated circuit, a logical synthesis with a lowered optimizing ability is executed by a logical synthesizing tool.
Also, Japanese Laid-Open Patent Publication No. 7-160748 discloses an estimation method on the basis of a hardware description language (hereinafter referred to as the “HDL”). In this method, a description unit in the HDL is identified, so that a delay time and a circuit scale of each description unit can be calculated.
However, such conventional methods have the following problems:
First, the performance estimation using the logical synthesizing tool has a problem that it takes a long period of time ranging from several tens minutes to several hours.
Also, in the method disclosed in the Japanese Laid-Open Patent Publication No. 7-160748, in obtaining the circuit area and the delay time of an operator included in the input HDL, a circuit configuration for realizing the operator is not considered. Therefore, it is impossible to search a design space represented by area-delay trade-off that a small circuit area leads to a large delay time and a small delay time leads to a large circuit area. Accordingly, the performance resulting from the logical synthesis cannot be precisely estimated.
Moreover, in the latter method, merely the delay time of a logic part in the integrated circuit is obtained. Therefore, in design of deep submicron, in which a line delay time can largely affect the operation speed of the integrated circuit, an error in the performance estimation can be disadvantageously large.
SUMMARY OF THE INVENTION
According to the present invention, the area and the timing of an integrated circuit at a register transfer level are estimated in consideration of area-performance trade-off by using estimation models for estimating performances of respective elements representing the integrated circuit at the register transfer level and driver models of drivers affecting a delay time of a line.
Specifically, the apparatus of this invention for estimating a performance of an integrated circuit in design at a register transfer level comprises an estimation library for storing estimation models used for estimating performances of respective elements representing the integrated circuit at the register transfer level; a driver library for storing driver models of modeled relationships between driving abilities and areas of drivers for driving a line; and trade-off estimation means for estimating a performance of a target integrated circuit at the register transfer level represented by using connections between the elements which satisfies a predetermined constraint, by applying the estimation models stored in the estimation library to respective elements of the target integrated circuit and by changing application of the driver models stored in the driver library if necessary.
In this apparatus, the trade-off estimation means predicts the performance, which satisfies a predetermined constraint, of the integrated circuit at the register transfer level represented by using connections between the elements by applying the estimation models stored in the estimation library to the respective elements and by changing the application of the driver models stored in the driver library if necessary. Accordingly, the area and the timing attained after the logical synthesis of the integrated circuit can be precisely estimated in consideration of the trade-off. In addition, since there is no need to perform the logical synthesis, the estimation requires a shorter period of time than that by using a conventional apparatus.
Preferably, the apparatus for estimating a performance of an integrated circuit further comprises parse tree allocation means for converting a representation by using parse trees of the target integrated circuit into a representation by using the connections between the elements through allocation of the elements whose estimation models are stored in the estimation library to respective nodes of the parse trees, and for inputting the representation by using the connections between the elements to the trade-off estimation means. Still preferably, the apparatus for estimating a performance of an integrated circuit further comprises parsing means for converting a description by a hardware description language of the target integrated circuit into the representation by using the parse trees through parsing, and for inputting the representation by using the parse trees to the parse tree allocation means.
Furthermore, in the apparatus for estimating a performance of an integrated circuit, the target integrated circuit has a hierarchical structure, the apparatus preferably further comprises floor plan means for determining placement of modules and line paths between the modules in each hierarchy of the target integrated circuit, and the trade-off estimation means preferably predicts a performance of said target integrated circuit which satisfies a predetermined constraint in consideration of a line delay time between the modules estimated on the basis of the line paths determined by the floor plan means.
Alternatively, in the method of this invention of estimating a performance of an integrated circuit in design at a register transfer level, estimation models for estimating performances of respective elements representing the integrated circuit at the register transfer level and driver models of modeled relationships between driving abilities and areas of drivers for driving a line are used, and the method comprises a trade-off estimating step of estimating a performance of a target integrated circuit at the register transfer level represented by using connections between the elements which satisfies a predetermined constraint by applying the estimation models to respective elements of the target integrated circuit and by changing application of the driver models if necessary.
In this method, the performance, which satisfies a predetermined constraint, of the integrated circuit at the register transfer level represented by using the connections between the elements can be estimated by applying the estimation models for estimating the performances of the respective elements and by appropriately changing the application of the driver models. Accordingly, the area and the timing attained after the logical synthesis of the integrated circuit can be precisely estimated. In addition, since there is no need to perform the logical synthesis, the estimation requires a shorter period of time than that by a conventional method.
Preferably, the method of estimating a performance of an integrated circuit further comprises, as a prior step, a step of converting a representation by using parse trees of the target integrated circuit into a representation by using the connections between the elements through allocation of the elements whose estimation models are prepared to respective nodes of the parse trees. Still preferably, the method of estimating a performance of an integrated circuit further comprises, as a prior step, a step of converting a descrip
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Sergent Douglas W.
Teska Kevin J.
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