Apparatus and method for equalizing received network signals usi

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression

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327336, 330302, 375229, H04B 110

Patent

active

061042366

ABSTRACT:
A network line equalizer includes a transconductance-controlled, tunable single zero high pass filter having a parasitic pole, and a single zero, single pole low pass filter, that eliminates the necessity of feedback loops or operational amplifiers. The tunable single zero high-pass filter includes a single zero impedance circuit, and first and second MOS transistors that output differential currents based on differential input signals and the impedance of the single zero impedance circuit. The MOS transistors act as source followers to convert the differential input voltage signals to respective differential current signals. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output a filtered pair of differential signals based on the impedance. The impedance of the single zero impedance circuit is implemented using CMOS transistors, enabling the impedance to be dynamically controlled by an external impedance controller. The single zero, single pole low pass filter includes first MOS transistors each having a first size (S1) and a gate for receiving the corresponding filtered differential voltage signal and in response outputting a first current signal. Low pass filters composed of MOS transistors output filtered voltage signals, and a set of second MOS transistors convert the filtered voltage signals to second current signals. The second MOS transistors have a size (S2) relative to the first size (S1) such that S2=S1(z-p)/p, where z is the zero and p is the pole of the low pass-filter.

REFERENCES:
patent: 4839542 (1989-06-01), Robinson
patent: 5227681 (1993-07-01), Koyama et al.
patent: 5559470 (1996-09-01), Laber et al.

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