Apparatus and method for entry allocation for a resource buffer

Details Apparatus and method for entry allocation for a resource buffer Apparatus and method for entry allocation for a resource buffer

1994-06-28

1996-02-06

Bowler, Alyssa H.

Boots, shoes, and leggings

395375, 364DIG2, 364939D, 36493141, 36493111, 36493155, G06F 300

Patent

active

054902800

ABSTRACT:
A method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. A deallocation vector of a reservation station is searched in order to locate, within one clock cycle, the vacancies within the reservation station for storage of instruction information associated with several issued operations. Vacancies are indicated by bits of the deallocation vector. A general static and dynamic approach are disclosed for performing the vacant entry identification at high speed within a single clock cycle. Alternate embodiments are disclosed, based on the general approach, that divide the deallocation vector into separate portions (consecutive bits or interleaved) and process each portion based on the general approaches. Rotating priority reference points within the deallocation vector may be used to vary the starting point for vacancy location. Further, the vacancy search can be limited to finding only consecutive vacancies. A superscalar microprocessor using the above may, within one clock cycle, schedule a group of instructions from the instruction decoder to the reservation station for subsequent execution.

REFERENCES:
patent: 5226126 (1993-06-01), McFarland et al.
patent: 5345569 (1994-09-01), Tran
Johsen; Superscalar Microprocessor Design; 1991; Chapter 7.
Dwyer; "A Multiple Out of Order Instruction Issuing System for SuperScalar Processors" Chapter 3 1991.
Val Popescu,et al.entitled, "The Metaflow Architecture," IEEE Micro, Jun. 1991,pp. 10-13, 63-73.

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