Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-01-10
2001-05-29
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000, C327S161000
Reexamination Certificate
active
06239634
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of analog circuit design. More particularly, the invention relates to an apparatus and method for ensuring the proper timing of a delay locked loop.
2. Description of the Related Art
Delay locked loops (“DLLs”) are used extensively in the fields of analog circuit design. With the increasingly stringent timing requirements of high performance computing and communications systems today, DLLs are also frequently being used for digital circuit designs (e.g., computer motherboards, high performance multimedia boards . . . etc).
The design goal of a DLL is to generate a clock which is delayed by a specified number of clock periods with respect to the input clock. For this reason, DLLs are commonly used in applications which require clock-skew elimination, clock/data recovery and multi-phase clock generation.
FIG. 1
illustrates a block diagram of a traditional DLL circuit. The input clock
105
, passes through a voltage controlled delay line (“VCDL”)
110
which generates a delayed version (“CLK
out
”)
120
of the input clock
105
. The delay in the VCDL
110
must be set precisely to some multiple of the input clock
105
period (e.g., 2×, 3×, etc., depending on the application). The delay through the VCDL
110
is controlled by a control voltage
115
. The higher the control voltage
115
, the shorter the delay between the input
105
and output
120
clocks.
The control voltage
115
(and, therefore, the amount of delay in the VCDL
110
) is modified by a feedback loop which consists of a phase detector
125
, a charge pump
130
and a capacitor
135
. The phase detector
125
detects the actual time delay (i.e., the phase difference) between the input clock
105
and the output clock
120
and, in response, causes the charge pump
130
to generate either a positive or a negative current pulse. A positive pulse charges the capacitor
135
, increasing the control voltage
115
, and a negative pulse discharges the capacitor
135
, decreasing the control voltage
115
. Accordingly, if the delay of the output clock
120
is too high, the charge pump
130
provides a positive current pulse (increasing the control voltage
115
), and if the delay is too short, the charge pump
130
provides a negative current pulse (decreasing the control voltage).
The feedback loop will settle when the delayed clock
120
is at the desired phase multiple of the input clock
105
(i.e. the delay is 1, 2, 3, etc. input clock periods).
SUMMARY OF THE INVENTION
A delay locked loop (DLL) is described comprising: a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal, said specified amount controlled by a control voltage applied to said delay unit; and a switch configured to clamp said control voltage to a predetermined value when said DLL is reset.
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Blakely & Sokoloff, Taylor & Zafman
Callahan Timothy P.
Parthus Technologies
Tra Quan
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