Apparatus and method for enhancing capacitance matching in a mul

Details Apparatus and method for enhancing capacitance matching in a mul Apparatus and method for enhancing capacitance matching in a mul

1991-06-17

1992-11-24

Logan, Sharon D.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341118, H03M 106, H03M 142

Patent

active

051666871

ABSTRACT:
Apparatus for enhancing capacitance matching in a multi-stage capacitor network of an A/D converter is provided. The stages are coupled to one another by a coupling capacitor having a top and bottom plate. The apparatus comprises a first shield overlying the capacitor network, where the shield is coupled to a known potential. A second shield is positioned over each of the coupling capacitors, where each second shield is separate from the first shield and coupled to the bottom plate of each respective coupling capacitor.

REFERENCES:
patent: 4799042 (1989-01-01), Confalonieri et al.
J. L. McCreary, et al., "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part I" IEEE Journal of Solid State Circuits, vol SC-10, No. 6, Dec. 1975, pp. 371-379.
Y. S. Yee, et al., "A Two-Stage Weighted Capacitor Network for D/A-A/D Conversion", IEEE Journal of Solid State Circuits, vol. SC-14, No. 4, Aug. 1979, pp. 778-781.
R. K. Hester et al., "Fully Differential ADC With Rail-to-Rail Common-Mode Range and Nonlinear Capacitor Compensation" IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 173-182.

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