Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
2008-04-22
2008-04-22
Patel, Niketa (Department: 2181)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C370S310000, C370S352000, C370S353000, C370S354000, C370S463000
Reexamination Certificate
active
09819997
ABSTRACT:
A method and apparatus for enhancing channel adapter performance that includes a host interface, a link interface, a packet processing engine, an address translation engine, and a completion queue engine. The host interface is connected to a memory by a local bus. The memory contains one or more completion queues and an event queue. The link interface is connected to a network. The packet processing engine moves data between the host interface and the link interface. The address translation engine translates a virtual address into a physical address of a translation protection table in the memory. The completion queue engine processes completion requests from the packet processing engine by writing the appropriate completion queue and/or event queue. The packet processing engine is not impacted by any address translation functionality, completion queue accesses, or event queue accesses thereby significantly enhancing the performance of a channel adapter.
REFERENCES:
patent: 6564271 (2003-05-01), Micalizzi et al.
patent: 6704831 (2004-03-01), Avery
Berry Frank L.
Collins Brian M.
Intel Corporation
Patel Niketa
Schwegman Lundberg & Woessner, P.A.
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