Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
1999-03-05
2001-06-05
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Instruction fetching
Reexamination Certificate
active
06243802
ABSTRACT:
FIELD OF THE INVENTION
The invention concerns an apparatus and method for encrypted instructions, especially during refetch operations.
BACKGROUND OF THE INVENTION
Central processing units (CPU's) of computer systems usually have address registers to store the addresses of the last A instructions read by the CPU. If there is a need to refetch one of the last A instructions, the address of this instruction is sent to the memory, causing the instruction to be refetched to the CPU. Often, an instruction is refetched if it causes an exception; the exception can be an error, unusual condition, or an external signal that sets a CPU status bit and thereby causes an interrupt.
There is a need to store information, i.e., data and instructions, in coded or ciphered or encrypted form. This can arise because of a desire to make the information opaque to unintended users or to conserve memory space through some means of redundancy elimination or compaction coding or for other reasons.
Storing information in coded or encrypted form causes several problems, among which is the need to decode the information when it is retrieved from the memory when it is to be processed by peripherals or other units that can only handle plain language (i.e., decoded) information. When coded information must be refetched there is a need to decode it again, thereby causing a waste of time and degradation of system performances.
A further problem occurs when a peripheral that is not connected to the output of the decoder needs information held in memory in coded form. This peripheral cannot directly read or process the coded information.
These problems are especially acute when information is refetched, because processing time is usually more critical in refetch operations, e.g., when an interrupt has occurred. For example, if an instruction causes an exception, so that an address of an instruction is refetched from a CPU address register, the refetched instruction will still be in coded form if it is refetched directly from memory and sent to, for example, a Load/Store unit within the CPU.
Accordingly, there is a continuing need for improved methods and apparatus for handling refetch operations and other operations where coded or encrypted information must be used multiple times.
As used herein the word “information” is intended to include any type of data or instructions or both. As used herein, the words encode, encrypt, encipher, and the words decode, decrypt and decipher, and related forms, are intended to include any form of coding for any purpose, including but not limited to obscuring meaning, compaction to occupy less space or transmission time, or any other information processing technique. The words encode, encipher and encrypt are intended to have the same meaning, and likewise for their inverse forms, e.g., decode, decipher and decrypt.
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J. Wang et al “The feasibility of using compression to increase memory system performance”. Mascots 94, proceedings of international workshop on modeling, analysis and simulation of computer and telecommunication systems, Jan. 31, 1994-Feb. 2, 1994, pp. 107-113.
Breternitz M J R et al, “Enhanced compression techniques to simplify program decompression and execution”, Proceedings. International conference on computer design VLSI in computers and processors, Austin, Texas, USA, Oct. 12-15, 1997, IEEE, pp. 170-176.
Baron Neri
Grobman Alexander
Sukonik Vitaly
Eng David Y.
King Robert L.
Motorola Inc.
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