Apparatus and method for emulation routine instruction issue

Details Apparatus and method for emulation routine instruction issue Apparatus and method for emulation routine instruction issue

1993-09-27

1994-11-01

Eng, David Y.

Boots, shoes, and leggings

3642624, 3649462, G06F 938, G06F 9455

Patent

active

053613899

ABSTRACT:
An apparatus for emulation routine instruction issue comprises a bus signal router, a state machine, a virtual program counter (VPC) circuit, an emulated program counter (EPC), a summing circuit, an opcode storage register, and a pointer storage register. The VPC circuit maintains the VPC value under the direction of the state machine. In response to a next instruction request issued by the central processing unit (CPU), the state machine outputs the VPC to an instruction address bus, transferring the host instruction stored at the address indicated by the VPC to the instruction bus for issue to the CPU. After a next host instruction request, the state machine updates the VPC value. Concurrent with the execution of the current emulation routine, the state machine prefetches the nest emulation routine pointer (NERP) by issuing DMA commands and commands to the EPC, the opcode storage means, and the pointer storage means. If the final host instruction in the current emulation routine has been reached, the state machine assigns the NERP to the VPC and outputs the VPC to the instruction address bus. A method for Emulation Routine Instruction Issue comprises the steps of determining if a next host instruction request has been made by the CPU; outputting the VPC to the instruction address bus; and updating the VPC; and prefetching the NERP concurrent with the execution of the host instructions in the current emulation routine.

REFERENCES:
patent: 4003033 (1977-01-01), O'Keefe
patent: 4179737 (1979-12-01), Kim
patent: 4791557 (1988-12-01), Angel et al.
patent: 4847753 (1989-07-01), Matsuo
patent: 4894772 (1990-01-01), Langendorf

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