Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Forming multiple superposed electrolytic coatings
Reexamination Certificate
2002-11-22
2003-10-28
Ryan, Patrick (Department: 1745)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Forming multiple superposed electrolytic coatings
C205S123000, C205S157000, C205S221000, C205S295000, C205S296000
Reexamination Certificate
active
06638410
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor. Devices which may be formed within the semiconductor include MOS transistors, bipolar transistors, diodes and diffused resistors. Devices which may be formed within the dielectric include thin-film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer. The devices utilized in each dice are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
Delays in propagation of electrical signals between devices on a single die limit the performance of integrated circuits. More particularly, these delays limit the speed at which an integrated circuit may process these electrical signals. Larger propagation delays reduce the speed at which the integrated circuit may process the electrical signals, while smaller propagation delays increase this speed. Accordingly, integrated circuit manufacturers seek ways in which to reduce the propagation delays.
For each interconnect path, signal propagation delay may be characterized by a time delay &tgr;. See E. H. Stevens,
Interconnect Technology
, QMC, Inc., July 1993. An approximate expression for the time delay, &tgr;, as it relates to the transmission of a signal between transistors on an integrated circuit is given below.
&tgr;
=RC[
1+(
V
sat
/RI
SAT
)]
In this equation, R and C are, respectively, an equivalent resistance and capacitance for the interconnect path and I
SAT
and V
SAT
are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path. The path resistance is proportional to the resistivity, &rgr;, of the conductor material. The path capacitance is proportional to the relative dielectric permittivity, K
e
, of the dielectric material. A small value of &tgr; requires that the interconnect line carry a current density sufficiently large to make the ratio V
sat
/RI
SAT
small. It follows therefore, that a low-&rgr; conductor which can carry a high current density and a low-K
e
dielectric must be utilized in the manufacture of high-performance integrated circuits.
To meet the foregoing criterion, copper interconnect lines within a low-K
e
dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most preferred interconnect structure. See “Copper Goes Mainstream: Low-k to Follow”,
Semiconductor International
, November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 &mgr;&OHgr;cm.; resistivities of aluminum-alloy films are in the range of 3.0 to 3.5 &mgr;&OHgr;cm.
Despite the advantageous properties of copper, it has not been as widely used as an interconnect material as one would expect. This is due, at least in part, to the difficulty of depositing copper metallization and, further, due to the need for the presence of barrier layer materials. The need for a barrier layer arises from the tendency of copper to diffuse into silicon junctions and alter the electrical characteristics of the semiconductor devices formed in the substrate. Barrier layers made of, for example, titanium nitride, tantalum nitride, etc., must be laid over the silicon junctions and any intervening layers prior to depositing a layer of copper to prevent such diffusion.
A number of processes for applying copper metallization to semiconductor workpieces have been developed in recent years. One such process is chemical vapor deposition (CVD), in which a thin copper film is formed on the surface of the barrier layer by thermal decomposition and/or reaction of gas phase copper compositions. A CVD process can result in conformal copper coverage over a variety of topological profiles, but such processes are expensive when used to implement an entire metallization layer.
Another known technique, physical vapor deposition (PVD), can readily deposit copper on the barrier layer with relatively good adhesion when compared to CVD processes. One disadvantage of PVD processes, however, is that they result in poor (non-conformal) step coverage when used to fill microstructures, such as vias and trenches, disposed in the surface of the semiconductor workpiece. For example, such non-conformal coverage results in less copper deposition at the bottom and especially on the sidewalls of trenches in the semiconductor devices.
Inadequate deposition of a PVD copper layer into a trench to form an interconnect line in the plane of a metallization layer is illustrated in FIG.
1
. As illustrated, the upper portion of the trench is effectively “pinched off” before an adequate amount of copper has been deposited within the lower portions of the trench. This results in an open void region that seriously impacts the ability of the metallization line to carry the electrical signals for which it was designed.
Electrochemical deposition of copper has been found to provide the most cost-effective manner in which to deposit a copper metallization layer. In addition to being economically viable, such deposition techniques provide substantially conformal copper films that are mechanically and electrically suitable for interconnect structures. These techniques, however, are generally only suitable for applying copper to an electrically conductive layer. As such, an underlying conductive seed layer is generally applied to the workpiece before it is subject to an electrochemical deposition process. Techniques for electrodeposition of copper on a barrier layer material have not heretofore been commercially viable.
The present inventors have recognized that there exists a need to provide copper metallization processing techniques that 1) provide conformal copper coverage with adequate adhesion to the barrier layer, 2) provide adequate deposition speeds, and 3) are commercially viable. These needs are met by the apparatus and processes of the present invention as described below.
BRIEF SUMMARY OF THE INVENTION
A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer has a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.
In accordance with a specific embodiment of the process, a copper metallization interconnects structure is formed. To this end, the ultra-thin seed layer is enhanced by subjecting the semiconductor workpiece to an electrochemical copper deposition process in which an alkaline bath having a complexing agent is employed. The copper complexing agent may be at least one complexing agent selected from a group consisting of EDTA, ED, and a polycarboxylic acid such as citric acid or salts thereof.
REFERENCES:
patent: 3267010 (1966-08-01), Creutz et al.
patent: 3328273 (1967-06-01), Creutz et al.
patent: 3664933 (1972-05-01), Clauss
patent: 3716462 (1973-02-01), Jensen
patent: 3770598 (1973-11-01), Creutz
patent: 3878066 (1975-04-01), Dettke et al.
patent: 3930963 (1976-01-01), Polichette et al.
patent: 4000046 (1976-12-01), Weaver
patent: 4134802 (1
Chen Linlin
Taylor Thomas
Parsons Thomas H.
Perkins Coie LLP
Ryan Patrick
Semitool Inc.
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