Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Involving measuring – analyzing – or testing
Reexamination Certificate
2002-11-25
2004-07-13
Nicolas, Wesley A. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Involving measuring, analyzing, or testing
C205S082000, C205S083000, C205S096000
Reexamination Certificate
active
06761812
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to the field of electroplating metal layers on workpieces suitable for the fabrication of integrated circuits, such as, for example, silicon wafers.
2. Description of the Related Art
In recent years, many efforts have been made in the art to develop methods and apparatuses for forming a layer of an electrically-conductive material filling a plurality of spaced-apart recesses formed in the surface of a substrate, wherein the exposed upper surface of the layer is substantially coplanar with non-recessed areas of the substrate surface. More particularly, methods and/or apparatuses have been developed in the art for performing “back-end” metallization of semiconductor high-speed integrated circuit devices having sub-micron dimensional design features and high conductivity interconnect features, wherein an attempt is made to achieve the complete filling of the recesses while facilitating subsequent planarization of the metallized surface by chemical mechanical polishing (CMP), increasing manufacturing throughput and improving product quality.
A commonly-employed method for forming metallization patterns such as are required for metallization processing of semiconductor wafers employs the so-called “damascene” technique. Generally, in such a process, recesses for forming metal lines for electrically connecting horizontally separated devices and/or circuits are created in a dielectric layer by conventional photolithography and etching techniques, and filled with metal, typically aluminum or copper. Any excess metal on the surface of the dielectric layer is then removed by, e.g., chemical mechanical polishing techniques, wherein a moving pad is biased against the surface to be polished, with a slurry containing abrasive particles (and other ingredients) being interpositioned therebetween.
FIGS. 1
a
-
1
c
schematically show, in a simplified cross-sectional view, a conventional damascene process sequence employing electroplating and CMP techniques for forming metallization patterns (illustratively of copper-based metallurgy but not limited thereto) on a semiconductor substrate
1
. In
FIG. 1
a
, a dielectric layer
3
with a surface
4
is located on the substrate
1
with a recess or trench
2
formed therein. An adhesion/barrier layer
7
and a nucleation/seed layer
8
are formed on the dielectric layer
3
.
A typical process flow may include the following steps. In a first step, the desired conductive pattern is defined as the recess or trench
2
formed (as by conventional photolithography and etching techniques) in the surface
4
of the dielectric layer
3
(e.g., a silicon oxide and/or nitride or an organic polymeric material) deposited or otherwise formed over the semiconductor substrate
1
. Next, the adhesion/barrier layer
7
comprising, e.g., titanium, tungsten, chromium, tantalum or tantalum nitride, and the overlying nucleation/seed layer
8
, (usually copper, or copper-based alloy) is subsequently deposited by well-known techniques, such as physical vapor deposition (PVD), chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD).
FIG. 1
b
shows the substrate
1
after deposition of the bulk metal layer
5
of copper or copper-based alloy by conventional electroplating techniques to fill the recess
2
. In order to ensure complete filling of the recess, the metal layer
5
is deposited as a blanket or overburden layer of excess thickness so as to overfill the recess
2
and cover the upper surface
4
of the dielectric layer
3
. Next, the entire excess thickness of the metal layer
5
over the surface
4
of the dielectric layer
3
, as well as the layers
7
and
8
, are removed by a CMP process.
FIG. 1
c
shows a metal portion
5
′ in the recess
2
with its exposed upper surface
6
substantially coplanar with the surface
4
of the dielectric layer
3
as a result of the CMP process.
FIG. 2
shows, in a simplified manner, a typical electroplating reactor
9
that may be used to form the metal layer
5
. The electroplating reactor
9
comprises a reaction chamber
10
adapted for containing an electroplating fluid
11
. A substrate holder
15
is configured to hold the substrate
1
facedown in the reaction chamber
10
. One or more contacts
12
are provided to connect the substrate surface to a plating power supply
13
. An anode
14
is disposed in the chamber
10
and is connected to the plating power supply
13
. For the sake of simplicity, means for establishing a fluid flow and a diffuser, as typically used in fountain-type reactors, are not shown in FIG.
2
. The substrate holder
15
and/or the anode
14
may be rotatable about an axis
1
′. Of course, reactors other than the reactor
9
depicted in
FIG. 2
may be used for the purpose of electroplating the metal layer
5
. For instance, reactors may be used in which the electroplating fluid is sprayed on the wafer or reactors may be used in which the wafer is immersed in an electroplating bath.
In operation, a voltage is applied between the anode
14
and the substrate
1
via the contacts
12
, wherein current paths form from the anode
14
via the fluid
11
, the surface of the substrate
1
, i.e., the seed layer
8
, and the contacts
12
to the power supply
13
. Among others, the deposition rate, at specific areas of the substrate
1
, depends on the amount of current flowing in each of the current paths defined by the individual contacts
12
.
The damascene technique as explained above with reference to
FIGS. 1
a
-
1
c
suffers from several drawbacks, at least some of which are caused by the non-uniformity of the metal layer
5
.
Shown in
FIG. 3
a
is the typical situation at the end of a prior art electroplating process. As is apparent from
FIG. 3
a
, the thickness of the metal layer
5
may notably vary. This is particularly disadvantageous when different portions of the substrate
1
including trenches
2
a
and
2
b
are covered by a layer having a non-uniform thickness. The non-uniformity of the metal layer
5
may result in a degradation of the metal trenches
2
a
,
2
b
in the subsequent CMP process.
As shown in
FIG. 3
b
, if the CMP process is stopped as soon as the portions of the metal layer
5
at the trenches
2
b
are removed, residuals of the layer
5
are left on the substrate
1
and may cause shorts or leakage currents between the metal lines
2
a
. As shown in
FIG. 3
c
, if, on the other hand, the CMP process is carried out until the portions of the layer
5
having greater thickness are removed and no metal residuals are left on the substrate, the metal in the metal lines
2
b
will be removed in excess. Accordingly, the cross-sectional dimensions of the metal lines
2
b
would be decreased, thereby adversely affecting the electrical and thermal conductivity of the metal lines
2
b.
Since the CMP process may also exhibit an “intrinsic” non-uniformity, which may contribute to the total degree of non-uniformity, the situation described above may become even worse and require a high degree of “safety” margins in the design rules.
Accordingly, in view of the problems explained above, it would be desirable to provide an electroplating method and apparatus that may solve or reduce one or more of the problems identified above. In particular, it would be desirable to provide a method and an apparatus for electroplating layers of conductive material on workpieces, thereby insuring a high controllability of the deposition process.
SUMMARY OF THE INVENTION
In particular, the present invention is based on the consideration that it is essential to monitor the individual current paths to obtain information about the uniformity of the plating process. Moreover, according to the inventors' finding, layers of a conductive material exhibiting a high degree of uniformity over the whole substrate surface can be electroplated by contacting the wafer at different positions and supplying curre
Marxsen Gerd
Preusse Axel
Advanced Micro Devices , Inc.
Nicolas Wesley A.
Williams Morgan & Amerson P.C.
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