Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1996-02-20
1999-10-05
Malzahn, David H.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
711220, G06F 750
Patent
active
059615800
ABSTRACT:
A linear address generation apparatus is provided which adds the segment base address to the displacement provided in the instruction while the instruction is being decoded. The linear and logical address generation are combined. Whereas linear address generation may have formerly required 2-3 clock cycles, 1-2 clock cycles may be achieved using the apparatus disclosed herein. The reduced latency in generating linear addresses may lead to reduced data access latency, and further may lead to increased performance in a microprocessor employing the apparatus. Performance increases are derived from the reduced number of clock cycles required for execution of memory accesses, and due to instructions dependent upon the memory accesses receiving data more quickly. For embodiments of the microprocessor employing the x86 microprocessor architecture, the apparatus additionally detects an arithmetic carry from low order bits of the addition to higher order bits of the addition. If the microprocessor is executing in 16 bit addressing mode, the logical address is truncated to 16 bits prior to adding the address to the 32 bit segment base address. Because the additions performed in this embodiment are 32 bit additions, the truncation to 16 bits is lost. Therefore, a carry from the low order 16 bits to the high order 16 bits is detected. If the instruction is executed in 16 bit addressing mode and a carry is detected, then the microprocessor causes an exception. The instruction is then handled by a microcode unit.
REFERENCES:
patent: 4373182 (1983-02-01), Schultz et al.
patent: 4409654 (1983-10-01), Wada et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5185871 (1993-02-01), Frey et al.
patent: 5204953 (1993-04-01), Dixit
patent: 5233553 (1993-08-01), Shak et al.
patent: 5274776 (1993-12-01), Senta
patent: 5345569 (1994-09-01), Tran
patent: 5408626 (1995-04-01), Dixit
patent: 5423013 (1995-06-01), Baum et al.
patent: 5434987 (1995-07-01), Abramson et al.
patent: 5511017 (1996-04-01), Cohen et al.
patent: 5517657 (1996-05-01), Rodgers et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5524263 (1996-06-01), Griffth et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5559975 (1996-09-01), Christie et al.
patent: 5568630 (1996-10-01), Killian et al.
patent: 5590297 (1996-12-01), Huck et al.
patent: 5590352 (1996-12-01), Zuraski, Jr. et al.
patent: 5612911 (1997-03-01), Timko
patent: 5615350 (1997-03-01), Hesson et al.
patent: 5655139 (1997-08-01), Thomson et al.
patent: 5664137 (1997-09-01), Abramson et al.
IBM Technical Disclosure Bulletin, "Dual Load/Store Unit With a Single Port Cache", vol. 38, No. 8, Aug. 1995. pp. 11-15.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Malzahn David H.
Merkel Lawerence J.
LandOfFree
Apparatus and method for efficiently calculating a linear addres does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for efficiently calculating a linear addres, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for efficiently calculating a linear addres will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1164949