Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1999-01-25
2003-09-02
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S522000, C345S537000, C345S547000
Reexamination Certificate
active
06614437
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data storage techniques, and relates more particularly to an apparatus and method for efficient memory utilization in an electronic system.
2. Description of the Background Art
Effective and efficient memory utilization is a significant consideration for designers, manufacturers, and users of electronic systems. Memory space for storage of data in electronic systems is often limited by physical constraints as well as by financial considerations. Many of the most effective and efficient electronic systems contain the smallest amount of memory necessary, and utilize that memory as efficiently as possible.
Such electronic systems vary widely, and may include digital video disc devices that reproduce feature films, video games, and other types of audio-visual entertainment, or set-top boxes for digital video broadcasting (DVB). Video data typically requires a large amount of digital data to encode the represented visual information. Such large amounts of digital data are typically compressed before being stored in a storage medium, such as a digital video disc (DVD). Video data may typically be encoded using various standard video compression techniques, for example JPEG or MPEG.
To display the video data stored on a DVD, the compressed digital data must be decoded. Video decoder systems perform a decoding process that depends on the compression technique used to compress the data. A decoding (or reconstruction) process typically reconstructs fields or frames of video from various pieces of data, including reference pictures, motion vectors, and error (or difference) coefficient data.
Video decoder systems typically utilize external system memory and blocks of internal memory to perform the reconstruction process. The various blocks of internal memory are typically assigned to store specific types of data. Efficient utilization of these specifically assigned blocks of internal memory improves the overall efficiency of the video decoder system. Manufacturers of such efficient systems will be able to produce a high quality product and provide it to consumers at a reasonable cost.
Video images are typically displayed at a high rate; for example thirty frames per second for interlaced scan images. Since reconstructing a single field or frame of video requires processing many pieces of data, a high display rate requires a correspondingly higher rate of data processing to create display images. The flow of data through internal memory must be managed as efficiently as possible to facilitate the high rate of data processing necessary in video decoder systems. Therefore, effective and efficient memory utilization remains a significant consideration for designers, manufacturers, and users of electronic systems.
SUMMARY OF THE INVENTION
In accordance with the present invention, an apparatus and method is disclosed for efficient memory utilization in an electronic system. The invention includes a memory divided into a plurality of equal-sized memory units, a data source, and an interface between the memory and the data source, which manages storage and retrieval of data in the memory. The data source generates a plurality of first data components and a plurality of second data components, each of the first data components containing more data than each of the second data components. Each memory unit is sized to contain one of the second data components.
In one embodiment of the present invention, the plurality of memory units is preferably configured as a continuous memory ring. The interface stores the data components sequentially in the memory ring as the data components are generated by the data source. Each type of data component does not have a specifically assigned location in the memory. The interface also retrieves the data components sequentially from the memory ring. A control module sends control signals to the interface to control read and write operations for the data components.
The control module also asserts a busy signal to the data source to halt generation of the data components when sufficient memory is not available. The control module de-asserts the busy signal to resume generation of the data components by the data source when sufficient memory becomes available.
In one embodiment, the electronic system comprises a video decoder system. The first data components comprise luminance data, and the second data components comprise chrominance data. The data source alternately generates luminance data components and chrominance data components, and each luminance data component contains twice as much data as each chrominance data component. The interface stores each luminance data component in two memory units and stores each chrominance data component in one memory unit.
In one embodiment, the interface monitors the location of each data component in the memory, and generates a write enable and a read enable in response to control signals from the control module. The interface also generates addresses for the data components in response to a control signal from the control module. The present invention thus efficiently and effectively implements efficient memory utilization in an electronic system.
REFERENCES:
patent: 4858173 (1989-08-01), Stewart et al.
patent: 4975880 (1990-12-01), Knierim et al.
patent: 5428766 (1995-06-01), Seaman
patent: 5489746 (1996-02-01), Suzuki et al.
patent: 5493589 (1996-02-01), Ibenthal
patent: 5568200 (1996-10-01), Pearlstein et al.
patent: 5602956 (1997-02-01), Suzuki et al.
patent: 5745791 (1998-04-01), Peek et al.
patent: 5818533 (1998-10-01), Auld et al.
patent: 6052490 (2000-04-01), Haskell et al.
patent: 6141744 (2000-10-01), Wing So
patent: 6275877 (2001-08-01), Duda
patent: 0696874 (1996-02-01), None
patent: 0825781 (1998-02-01), None
patent: 2316824 (1998-03-01), None
patent: 9746023 (1997-12-01), None
Kou Chon In
Tohara Tomonari
Bella Matthew C.
Koerner Gregory J.
Monestime Mackly
Simon & Koerner LLP
Sony Corporation
LandOfFree
Apparatus and method for efficient memory utilization in an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for efficient memory utilization in an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for efficient memory utilization in an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3037168