Apparatus and method for efficient carry skip incrementation

Details Apparatus and method for efficient carry skip incrementation Apparatus and method for efficient carry skip incrementation

1995-01-04

1996-09-10

Envall, Jr., Roy N.

Boots, shoes, and leggings

364787, G06F 750

Patent

active

055555179

ABSTRACT:
A carry-skip incrementor mitigating propagation delay experienced by conventional ripple carry incrementors without employing a substantially greater device count, includes a plurality of circuit blocks operating in combination with a plurality of logic gates. Each circuit block receives as input a varying number of data bits of an input operand and a carry signal and thereafter, generates a product signal and real bit sums corresponding to these data bits. The plurality of logic gates are arranged such that each logic gate receives as input the product signal from a first adjacent circuit block and the carry signal and outputs the carry signal for a second adjacent circuit block. The carry signal is active if the product signal and the carry signal are active. Thus, the delay associated with the first adjacent circuit block is bypassed in favor of the delay associated with the logic gate.

REFERENCES:
patent: 4905180 (1990-02-01), Kumar
patent: 5027310 (1991-06-01), Dalrymple
patent: 5136539 (1992-08-01), Kumar
patent: 5198993 (1993-03-01), Makakura

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