Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
2000-02-22
2003-10-28
Ghayour, Mohammad H. (Department: 2734)
Pulse or digital communications
Receivers
Angle modulation
C375S279000, C375S283000
Reexamination Certificate
active
06639953
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to binary demodulators, and is particularly directed to improvements in the efficiency of binary demodulators for data conveyed via binary phase shift keying.
BACKGROUND OF THE INVENTION
Binary phase shift keying (BPSK) is one method utilized to convey binary data. In a BPSK system, sequential data bits are represented by phase shifts of a carrier frequency within a signal (i.e., a BPSK signal) that is output from a transmitter. For BPSK receivers, several techniques are known to demodulate BPSK signals and discern the information conveyed therein.
In one type of BPSK demodulation, a BPSK receiver generates I and Q channels. Each channel is independently sampled at a sample rate to provide a group of sample values. Each group of sample values is intended to be associated with one of the successive bits that are conveyed via the BPSK signal. An algorithm is performed to process each group of samples (i.e., the group of samples for the I channel and/or the group of samples for the Q channel) to make a determination as to whether the respective bit should be accorded a bit value of “1” or a bit value of “0”. The algorithm is repeated for each bit.
The rate at which a BPSK receiver can demodulate information is dependent upon the speed at which the algorithm is performed within the receiver. Thus, the demodulation rate is directly related to the processing capabilities within the BPSK receiver. Small and/or low cost BPSK receivers may have associated limitations upon their ability (e.g., speed) at which they can process BPSK signals that convey data.
Many communication systems that currently exist utilize binary data communication. One particular type of such communication systems is the group of remote convenience systems that permit remote control of certain functions. One example type of a remote convenience system is for remotely controlling vehicle functions. Other example types of remote convenience systems include garage door opener systems and entry light activation systems.
Focusing on the remote convenience vehicle systems, remotely controlled vehicle functions include locking and unlocking functions of one or more vehicle doors. A remote convenience system that permits remote locking and unlocking is commonly referred to as a remote keyless entry system. Such remote vehicle systems may provide for control of other vehicle functions. For example, a remote vehicle alarm function, a remote vehicle locator function, and a remote vehicle engine start function may also be provided.
Known remote convenience vehicle systems include a receiver/controller unit mounted in an associated vehicle and at least one portable hand-held unit located remote from the receiver/controller unit. Typically, the portable unit has a relatively small size that permits carrying the portable unit within a pocket, within a purse, or on a key chain.
SUMMARY OF THE INVENTION
In accordance with one aspect, the present invention provides a binary phase shift key demodulator for a signal conveying bits. The demodulator includes means for associating an I, Q vector with a bit. Means assigns a first group of vector angles to a first binary value, assigns a second group of vector angles to a second binary value, and assigns a third group of vector angles as an indeterminate binary value. Means interprets the bit as the first binary value if the associated vector is within the first group. Means interprets the bit as the second binary value if the associated vector is within the second group. Means processes information associated with the bit to determine whether to interpret the bit as the first or second binary value if the associated vector is within the third group and for accordingly interprets the bit.
In accordance with another aspect, the present invention provides a binary phase shift key demodulator for a signal conveying bits. The demodulator includes means for associating an I, Q vector to a reference bit. Means associates an I, Q vector to a subsequent bit. Means interprets the subsequent bit as a first binary value if the vector associated with the subsequent bit is within a first range of vector angles from the vector associated with the reference bit. Means interprets the subsequent bit as a second binary value if the vector associated with the subsequent bit is outside of a second range of vector angles from the vector associated with the reference bit. Means processes information associated with the second bit to determine whether to interpret the subsequent bit as the first or second binary value if the vector associated with the subsequent bit is outside of the first range of angles and within the second range of angles from the vector associated with the reference vector and for accordingly interpreting the bit.
In accordance with another aspect, the present invention provides a method of binary phase shift key demodulation for a signal conveying bits. An I, Q vector is associated with a bit. A first group of vector angles is assigned to a first binary value. A second group of vector angles is assigned to a second binary value. A third group of vector angles is assigned as an indeterminate binary value. The bit is interpreted as the first binary value if the associated vector is within the first group. The bit is interpreted as the second binary value if the associated vector is within the second group. Information associated with the bit is processed to determine whether to interpret the bit as the first or second binary value if the associated vector is within the third group, and the bit is accordingly interpreted.
In accordance with still another aspect, the present invention provides a method of binary phase shift key demodulation for a signal conveying bits. An I, Q vector is associated to a reference bit. An I, Q vector is associating to a subsequent bit. The subsequent bit is interpreted as a first binary value if the vector associated with the subsequent bit is within a first range of vector angles from the vector associated with the reference bit. The subsequent bit is interpreted as a second binary value if the vector associated with the subsequent bit is outside of a second range of vector angles from the vector associated with the reference bit. Information associated with the subsequent bit is processed to determine whether to interpret the subsequent bit as the first or second binary value if the vector associated with the subsequent bit is outside the first range of angles and within the second range of angles from the vector associated with the reference vector, and the bit is accordingly interpreted.
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Ghayour Mohammad H.
Tarolli, Sundheim Covell & Tummino L.L.P.
TRW Inc.
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